JEDEC宣布了一项新标准SPHBM4 (JESD330-4)，旨在通过允许在高带宽内存 (HBM) 的标准封装中使用HBM来普及HBM。这项新标准允许在专门的、供应受限的高级封装设施之外进行HBM组装，有可能使HBM能够用于中端AI芯片、网络硅和游戏GPU。SPHBM4通过减少引脚数量同时将信号速度提高四倍来实现这一目标，这也需要使用更高层数的基板，并增加了芯片封装占位符的物理尺寸，从而推动了基板材料的需求和定价。 AI
影响 这项新标准可以降低高性能内存的成本，并增加其在更广泛的AI加速器和相关硬件中的可用性。
排序理由 一项新行业标准的发布，该标准对AI芯片制造和组件可及性产生了重大影响。
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The Bottom Line: SPHBM4 shifts the complex engineering burden of AI chips. Instead of buying a hyper-expensive, proprietary "Silicon Interposer + ABF Substrate" combo, chipmakers will shift entirely to buying ultra-large, high-layer ABF or even pull forward the adoption of glass
🟠 It "democratizes" HBM. Right now, HBM is locked behind a massive bottleneck: only a few specialized foundries have the advanced packaging tech (like TSMC CoWoS) to build them. This keeps HBM restricted to ultra-premium AI accelerators. SPHBM4 changes the game. By allowing
🟠 It shoots layer counts through the roof. Moving 32 Gbps signals directly across an organic substrate is an electrical nightmare. To prevent data corruption and electromagnetic interference, you can't just use a basic low layer count ABF substrate. SPHBM4 will force the use ht…
🟠 It blows up the physical size of the substrate. Traditional HBM must sit microscopic millimeters away from the GPU because wide parallel signals degrade instantly over distance. Because SPHBM4 uses high-speed serial lanes, memory can sit up to 20mm away. This extra breathing
The idea is simple: maintain HBM4 performance while drastically reducing the reliance on expensive, supply-constrained advanced packaging. How? By slashing the pin count to 1/5th but quadrupling signal speeds to 32 Gbps. This allows HBM-level bandwidth using standard substrates,…
This last week JEDEC announced a new standard for SPHBM4: Standard Package High Bandwidth Memory (JESD330-4). It utilizes the same DRAM stacks as HBM4, but swaps in a different buffer die. The goal? Enable HBM assembly in standard packaging and break the AI Advanced Packaging ht…