Arch AI-native HDL simplifies hardware design with LLM generation

Researchers have introduced Arch, a novel AI-native hardware description language designed for micro-architecture specification and AI-assisted code generation. Arch incorporates first-class constructs for common hardware structures, converting clock and reset analysis into compile-time typing rules for enhanced safety. The language's design prioritizes AI generatability, featuring a grammar and schema that allow Large Language Models to produce structurally correct and type-safe Arch code from natural language specifications. The compiler outputs SystemVerilog and automatically generates safety properties for formal verification. AI

影响 New hardware description language could streamline AI chip design and verification processes.

排序理由 Academic paper introducing a new hardware description language with AI-assisted code generation capabilities.

在 arXiv cs.CL 阅读 →

• cocotb
• LLM
• Shuqing Zhao
• Sky130
• SMT-LIB2
• SystemVerilog
• Verilator
• VerilogEval
• Yosys

• 论文
• 基础设施

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