English(EN) LLM Agent-Based Design of RISC-V CPUs with FPGA-in-the-Loop Evaluation

LLM智能体设计RISC-V CPU并进行FPGA评估，加速开发进程

作者 PulseAugur 编辑部 · [1 个来源] · 2026-10-31 04:00

研究人员开发了一个新的环境，使用LLM智能体和FPGA在环评估来设计RISC-V CPU。与传统的RTL仿真相比，这种方法显著加快了设计和决策过程。该系统被用于将一个单周期RV32I核开发成一个三宽乱序RV32IM核，在Artix-7 FPGA上以130 MHz实现了5.61 CoreMark/MHz。对于8000次CoreMark迭代运行，该FPGA评估比RTL仿真快9.6倍，并成功识别了较短诊断测试遗漏的性能下降。 AI

影响通过利用LLM和FPGA进行快速原型设计和评估，加速了硬件设计周期。

排序理由学术论文，详细介绍了CPU设计的一种新颖方法。[lever_c_demoted from research: ic=1 ai=1.0]

在 arXiv cs.AI 阅读 →

AI 生成摘要 · Google Gemini · 来自 1 个来源。我们如何撰写摘要 →

本文如何被排名

Signal score: 0 / 100; Composite score across the factors below. Higher = stronger signal that this story matters right now.
Newsworthiness bucket: Tool; 学术论文，详细介绍了CPU设计的一种新颖方法。[lever_c_demoted from research: ic=1 ai=1.0]
Source corroboration: Single-source cluster; Only one publisher covered this so far. Single-source stories can still rank when the publisher is high-authority, but they lack cross-source corroboration.
Topics: paper, infra; Editorial topic classification. Feeds into how the story surfaces on /topic/<slug> hub pages and into the per-entity coverage mix.
AI-industry relevance: High; Clearly on-topic for AI-industry coverage.
Story freshness: 3 days old; Aged out of breaking-news scoring windows; ranking reflects the durable signal from the full source set.

完整方法见我们的编辑标准。

报道来源 [1]

arXiv cs.AI TIER_1 English(EN) · Leo Itoh, Junichiro Kadomoto · 2026-10-31 04:00

基于LLM智能体的RISC-V CPU设计与FPGA在环评估

arXiv:2610.39570v1 Announce Type: cross Abstract: Long-run RTL simulation of CPU candidates can take hours, while short diagnostic runs may miss performance degradation that emerges later in execution. This evaluation cost can delay design decisions in LLM-agent-based CPU develop…

本文如何被排名

报道来源 [1]

基于LLM智能体的RISC-V CPU设计与FPGA在环评估

相关实体

相关话题