English(EN) SkyEgg: Heterogeneity-Aware Hardware Synthesis via Equality Saturation

SkyEgg 框架通过代数规则优化 FPGA 硬件综合

作者 PulseAugur 编辑部 · [1 个来源] · 2026-09-15 04:00

研究人员开发了 SkyEgg，一个旨在更好地利用现代现场可编程门阵列 (FPGA) 异构性的新硬件综合框架。与先前顺序处理资源的框架不同，SkyEgg 将代数重写规则与目标特定的硬件映射和配置相结合。这种方法允许更全面地探索实现选择，从而能够联合优化等价形式、资源映射和调度以最小化延迟。在评估中，SkyEgg 相较于 Vitis HLS 和 Altera HLS 分别实现了平均 3.12 倍和 3.18 倍的显著加速。 AI

排序理由该集群描述了一篇关于新型硬件综合框架的新学术论文。[lever_c_demoted from research: ic=1 ai=0.4]

在 arXiv cs.CL 阅读 →

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本文如何被排名

Signal score: 6 / 100; Composite score across the factors below. Higher = stronger signal that this story matters right now.
Newsworthiness bucket: Tool; 该集群描述了一篇关于新型硬件综合框架的新学术论文。[lever_c_demoted from research: ic=1 ai=0.4]
Source corroboration: Single-source cluster; Only one publisher covered this so far. Single-source stories can still rank when the publisher is high-authority, but they lack cross-source corroboration.
Topics: paper, infra; Editorial topic classification. Feeds into how the story surfaces on /topic/<slug> hub pages and into the per-entity coverage mix.
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Story freshness: Breaking (< 6h); Fresh story with cross-source coverage still developing. Ranking may shift as more sources report.

完整方法见我们的编辑标准。

报道来源 [1]

arXiv cs.CL TIER_1 English(EN) · Yuyang Zou, Youwei Xiao, Yitian Sun, Yun Liang · 2026-09-15 04:00

SkyEgg：异构感知硬件综合通过等式饱和

arXiv:2511.15323v2 Announce Type: replace-cross Abstract: Hardware synthesis is a key interface between high-level programs and accelerator designs. Modern FPGAs increasingly expose heterogeneity in resource functionality and timing configurability. Exploiting these resources req…

本文如何被排名

报道来源 [1]

SkyEgg：异构感知硬件综合通过等式饱和

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