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English(EN) 🟠 The challenge is co-optimizing SI and PI at the same time. Line width, spacing, ground placement, via location, PDN plane shape, and routing density all move

SemiAnalysis在ECTC上详细介绍了RDL集成挑战和GUC的STCO流程

作者 PulseAugur 编辑部 · [3 个来源] ·

SemiAnalysis在ECTC上讨论了芯片集成和信号完整性方面的进展，强调了优化RDL（重布线交付）技术的复杂性。Global Unichip Corporation (GUC)展示了一种用于CoWoS-R风格UCIe-A集成的实际STCO流程，该流程涉及复杂的预布局和后布局电磁仿真。讨论强调，在高数据速率下，RDL的物理几何形状对于通道性能至关重要，需要仔细调整多个层和结构以增强带宽和信号完整性。 AI

影响 强调了对高性能计算和AI硬件至关重要的芯片集成和信号完整性方面的进展。

排序理由 该集群讨论了在会议上提出的芯片集成和信号完整性方面的技术进展和挑战。

在 X — SemiAnalysis 阅读 →

AI 生成摘要 · Google Gemini · 来自 3 个来源。 我们如何撰写摘要 →

SemiAnalysis在ECTC上详细介绍了RDL集成挑战和GUC的STCO流程

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该集群讨论了在会议上提出的芯片集成和信号完整性方面的技术进展和挑战。
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infra, product
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报道来源 [3]

  1. X — SemiAnalysis TIER_1 English(EN) · SemiAnalysis_ ·

    🟠 同时优化SI和PI的挑战。线宽、间距、接地放置、过孔位置、PDN平面形状和布线密度都会移动

    🟠 The challenge is co-optimizing SI and PI at the same time. Line width, spacing, ground placement, via location, PDN plane shape, and routing density all move insertion loss, return loss, crosstalk, impedance peaks, and power noise. Check out our newsletter on ECTC 2026

  2. X — SemiAnalysis TIER_1 English(EN) · SemiAnalysis_ ·

    🟠 关键在于 RDL 不仅仅是“线缆和聚合物”。在 16 至 36 GT/s 时，几何形状成为通道的一部分。GUC 使用 GSG 交叉传输

    🟠 The key point is that RDL is not just “wires and polymers.” At 16 to 36 GT/s, the geometry becomes part of the channel. GUC uses GSG-interleaved transmission lines, where ground shielding traces surround the signal lines to improve isolation and help skew compensation. The

  3. X — SemiAnalysis TIER_1 English(EN) · SemiAnalysis_ ·

    在ECTC展会上，GUC展示了用于CoWoS-R风格UCIe-A集成的实用STCO流程，实现了从预布局2D电磁仿真探索到后布局3D电磁提取的转变

    At ECTC, GUC showed a practical STCO flow for CoWoS-R style UCIe-A integration, moving from pre-layout 2D EM exploration to post-layout 3D EM extraction, transient eye simulation, PDN impedance analysis, and final power-aware SI signoff. (1/3)🧵 https://t.co/gwRP5u4su9

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