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English(EN) Post-silicon era gets closer as industry giants crack the 2D transistor scaling bottleneck with breakthrough tech — imec, ASML, and TSMC fab complementary 2D-ma

imec、ASML、台积电实现2D晶体管50nm间距

作者 PulseAugur 编辑部 · [2 个来源] ·

imec、ASML和台积电已成功在300mm晶圆上制造了互补型2D材料晶体管，实现了50nm的间距。这一突破将n型和p型晶体管与原子级薄的2D沟道集成在一起，是克服硅尺寸限制的重要一步。该工艺利用单次极紫外（EUV）曝光打印出短至28nm的沟道，94%的晶体管功能正常并表现出高开关电流比。通过集成两种极性并在标准生产设备上实现，利用新颖的“反向”薄膜晶体管流程解决接触电阻问题，这一成就标志着2D晶体管尺寸扩展的一个里程碑。 AI

影响 这一晶体管技术的进步可能为未来更强大、更高效的人工智能硬件奠定基础。

排序理由 半导体制造领域涉及多家行业巨头的研究里程碑。

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imec、ASML、台积电实现2D晶体管50nm间距

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半导体制造领域涉及多家行业巨头的研究里程碑。
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报道来源 [2]

  1. Tom's Hardware TIER_1 English(EN) · Luke James ·

    后硅时代临近，行业巨头用突破性技术攻克二维晶体管的尺寸瓶颈——imec、ASML和台积电在300毫米晶圆上以50纳米间距制造互补性二维材料晶体管

    Imec, ASML, and TSMC have integrated both n-type and p-type transistors with atomically thin 2D channels on a single 300mm wafer.

  2. Mastodon — mastodon.social TIER_1 English(EN) · [email protected] ·

    后硅时代临近，行业巨头凭借突破性技术攻克二维晶体管的尺寸缩小瓶颈——imec、ASML 和 TSMC 联合开发互补性二维材料制造工艺

    Post-silicon era gets closer as industry giants crack the 2D transistor scaling bottleneck with breakthrough tech — imec, ASML, and TSMC fab complementary 2D-material transistors at 50nm pitch on … Imec, ASML, and TSMC have integrated both n-type and p-type transistors with atomi…

    链接 tomshardware.com/…/imec-asml-and-tsmc-bui… tomshardware.com/tech-industry

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