English(EN) Toward Autonomous RTL and Synthesis Optimization: Benchmarking and Self-Improving Agents

AI智能体自动化硬件设计，提升关键指标

作者 PulseAugur 编辑部 · [1 个来源] · 2026-11-11 05:00

研究人员开发了Dr. RTL，一个旨在自动化和优化硬件寄存器传输级（RTL）设计过程的多智能体框架。该框架通过学习可重用的优化技能持续改进，在20个真实RTL设计中，平均最差负时序裕量（WNS）提高了21%，总负时序裕量（TNS）提高了17%，同时面积减少了6%。该论文还探讨了智能体驱动的综合脚本调优，并设想了未来将架构、RTL和电子设计自动化（EDA）算法设计空间整合的AI原生设计自动化。 AI

影响这项研究展示了AI在显著提高硬件设计效率和性能方面的潜力，有望加速芯片开发周期。

排序理由介绍用于硬件设计优化的新AI框架的研究论文。[lever_c_demoted from research: ic=1 ai=1.0]

在 arXiv cs.AI 阅读 →

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报道来源 [1]

arXiv cs.AI TIER_1 English(EN) · Wenji Fang, Yao Lu, Jinghua Wang, Zhiyao Xie · 2026-11-11 05:00

迈向自主 RTL 和综合优化：基准测试和自改进代理

arXiv:2611.13713v1 Announce Type: new Abstract: Recent advances in large language models (LLMs) and autonomous agents are creating new opportunities for hardware design optimization. This paper examines three connected directions toward autonomous RTL and synthesis optimization: …

本文如何被排名

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迈向自主 RTL 和综合优化：基准测试和自改进代理

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