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English(EN) Formally Verified Synthesizable Floating-Point Data Types in ARCH HDL

LLM 生成的 ARCH HDL 可验证浮点类型

作者 PulseAugur 编辑部 · [1 个来源] ·

研究人员为 ARCH 硬件描述语言开发并验证了浮点数据类型，该类型专为语言模型生成而设计。该系统确保了可综合的 SystemVerilog、SMT-LIB 和 Lean 4 证明模型在比较、转换和算术运算等运算符之间的一致性。对较简单的运算符进行了详尽的验证，而复杂的基于乘法的运算则根据四舍五入到最近偶数的规范证明了其正确性，并针对性能和流水线化进行了优化。 AI

影响 使 AI 模型能够生成更可靠的硬件设计，从而可能加快硬件开发周期。

排序理由 详细介绍硬件描述语言组件形式化验证的学术论文。[lever_c_demoted from research: ic=1 ai=1.0]

在 arXiv cs.CL 阅读 →

AI 生成摘要 · Google Gemini · 来自 1 个来源。 我们如何撰写摘要 →

LLM 生成的 ARCH HDL 可验证浮点类型

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详细介绍硬件描述语言组件形式化验证的学术论文。[lever_c_demoted from research: ic=1 ai=1.0]
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报道来源 [1]

  1. arXiv cs.CL TIER_1 English(EN) · Shuqing Zhao ·

    ARCH HDL 中形式化验证的可综合浮点数据类型

    arXiv:2607.23715v1 Announce Type: new Abstract: We report the design and end-to-end verification of first-class IEEE-754 binary32 (FP32) and bfloat16 (BF16) arithmetic for ARCH, a hardware description language intended to be generated by language models. Every operator - comparis…

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