研究人员开发了SMART，一个结合了机器学习和蒙特卡洛模拟的新框架，用于加速数字电路中晶体管老化和工艺变化的分析。该方法使用随机森林回归和贝叶斯优化来预测门延迟分布，显著减少了分析时间并保持了高精度。SMART旨在为设计更可靠的数字系统提供可扩展的解决方案，以解决深纳米CMOS技术中传统仿真方法的局限性。 AI
影响 通过减少晶体管老化和工艺变化的分析时间，加速了可靠数字系统的设计空间探索。
排序理由 该集群描述了一篇学术论文中提出的新颖框架，该框架使用机器学习技术分析数字电路的可靠性。
AI 生成摘要 · Google Gemini · 来自 3 个来源。 我们如何撰写摘要 →
arXiv:2607.05187v1 Announce Type: new Abstract: As CMOS technology scales into the deep nanometer regime, digital circuit reliability is increasingly threatened by the combined stochastic effects of Bias Temperature Instability (BTI) and Process Variation (PV). Traditional reliab…
As CMOS technology scales into the deep nanometer regime, digital circuit reliability is increasingly threatened by the combined stochastic effects of Bias Temperature Instability (BTI) and Process Variation (PV). Traditional reliability analysis methods, which rely on computatio…
As CMOS technology scales into the deep nanometer regime, digital circuit reliability is increasingly threatened by the combined stochastic effects of Bias Temperature Instability (BTI) and Process Variation (PV). Traditional reliability analysis methods, which rely on computatio…