Arch AI-native HDL simplifies hardware design with LLM generation

Researchers have introduced Arch, a novel AI-native hardware description language designed for micro-architecture specification and AI-assisted code generation. Arch incorporates first-class constructs for common hardware structures, converting clock and reset analysis into compile-time typing rules for enhanced safety. The language's design prioritizes AI generatability, featuring a grammar and schema that allow Large Language Models to produce structurally correct and type-safe Arch code from natural language specifications. The compiler outputs SystemVerilog and automatically generates safety properties for formal verification. AI

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IMPACT New hardware description language could streamline AI chip design and verification processes.

RANK_REASON Academic paper introducing a new hardware description language with AI-assisted code generation capabilities.

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• Arch
• SystemVerilog
• LLM
• Verilator
• SMT-LIB2
• Yosys
• OpenSTA
• Sky130
• VerilogEval
• CVDP
• cocotb
• Shuqing Zhao

• paper
• infra