VerilogEval
PulseAugur coverage of VerilogEval — every cluster mentioning VerilogEval across labs, papers, and developer communities, ranked by signal.
3 day(s) with sentiment data
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LLMs struggle with RTL coding for hardware design, hitting knowledge limits
A new research paper explores the limitations of large language models (LLMs) in hardware design, specifically in translating sequential programming knowledge into the parallel logic required for Register-Transfer Level…
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New LLM tools enhance hardware design and data generation
Researchers are developing new methods to improve the use of large language models (LLMs) for hardware design, specifically for generating Register Transfer Level (RTL) code. One approach, LLM4RTL, uses a tool-assisted …
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New framework steers LLMs to generate more accurate RTL code
Researchers have developed CASS-RTL, a novel framework designed to improve the accuracy of large language models (LLMs) in generating hardware description language (HDL) code, specifically Register-Transfer Level (RTL).…
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New framework formalizes LLM-generated hardware designs for improved correctness
Researchers have developed CktFormalizer, a framework that uses Lean 4 to improve the generation of hardware descriptions from natural language by large language models. This system employs dependent types to catch comm…
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LEGO platform enables LLM skill-based front-end design generation
Researchers have introduced LEGO, a novel platform designed to enhance front-end design generation for electronic design automation (EDA) using large language models. This system breaks down the design process into six …
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TimingLLM predicts post-synthesis timing from Verilog with high accuracy
Researchers have developed TimingLLM, a novel two-stage framework designed to predict post-synthesis timing in Verilog code without requiring synthesis tools. The first stage employs a fine-tuned LLM to generate structu…
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Arch AI-native HDL simplifies hardware design with LLM generation
Researchers have introduced Arch, a novel AI-native hardware description language designed for micro-architecture specification and AI-assisted code generation. Arch incorporates first-class constructs for common hardwa…