Yosys
PulseAugur coverage of Yosys — every cluster mentioning Yosys across labs, papers, and developer communities, ranked by signal.
2 day(s) with sentiment data
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Verified floating-point types for ARCH HDL generated by LLMs
Researchers have developed and verified floating-point data types for the ARCH hardware description language, designed for generation by language models. The system ensures consistency across synthesizable SystemVerilog…
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New benchmark CLOSER-Bench evaluates AI agents in hardware design closure
Researchers have introduced CLOSER-Bench, a new evaluation protocol designed to assess the capabilities of AI agents in hardware engineering tasks. This benchmark focuses on budgeted cross-stage design closure, integrat…
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New framework enhances LLM-generated Verilog with feedback and skill evolution
Researchers have developed Verilog-Evolve, a novel framework designed to enhance the generation of Verilog code using large language models. This system moves beyond isolated sampling and functional checking by incorpor…
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Arch AI-native HDL simplifies hardware design with LLM generation
Researchers have introduced Arch, a novel AI-native hardware description language designed for micro-architecture specification and AI-assisted code generation. Arch incorporates first-class constructs for common hardwa…