ENTITY
Yosys
Yosys
PulseAugur coverage of Yosys — every cluster mentioning Yosys across labs, papers, and developer communities, ranked by signal.
Total · 30d
2
2 over 90d
Releases · 30d
0
0 over 90d
Papers · 30d
2
2 over 90d
TIER MIX · 90D
TOPICS
RECENT · PAGE 1/1 · 2 TOTAL
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New framework enhances LLM-generated Verilog with feedback and skill evolution
Researchers have developed Verilog-Evolve, a novel framework designed to enhance the generation of Verilog code using large language models. This system moves beyond isolated sampling and functional checking by incorpor…
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Arch AI-native HDL simplifies hardware design with LLM generation
Researchers have introduced Arch, a novel AI-native hardware description language designed for micro-architecture specification and AI-assisted code generation. Arch incorporates first-class constructs for common hardwa…