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Verified floating-point types for ARCH HDL generated by LLMs

By PulseAugur Editorial · [1 sources] ·

Researchers have developed and verified floating-point data types for the ARCH hardware description language, designed for generation by language models. The system ensures consistency across synthesizable SystemVerilog, SMT-LIB, and Lean 4 proof models for operators like comparisons, conversions, and arithmetic operations. Exhaustive verification was performed for simpler operators, while complex multiplier-based operations were proven correct against a round-to-nearest-even specification, with optimizations for performance and pipelineability. AI

IMPACT Enables more reliable hardware design generation from AI models, potentially speeding up hardware development cycles.

RANK_REASON Academic paper detailing formal verification of hardware description language components. [lever_c_demoted from research: ic=1 ai=1.0]

Read on arXiv cs.CL →

AI-generated summary · Google Gemini · from 1 sources. How we write summaries →

Verified floating-point types for ARCH HDL generated by LLMs

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Academic paper detailing formal verification of hardware description language components. [lever_c_demoted from research: ic=1 ai=1.0]
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COVERAGE [1]

  1. arXiv cs.CL TIER_1 English(EN) · Shuqing Zhao ·

    Formally Verified Synthesizable Floating-Point Data Types in ARCH HDL

    arXiv:2607.23715v1 Announce Type: new Abstract: We report the design and end-to-end verification of first-class IEEE-754 binary32 (FP32) and bfloat16 (BF16) arithmetic for ARCH, a hardware description language intended to be generated by language models. Every operator - comparis…

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