新的HGQ-LUT和da4ml方法加速DNN训练和FPGA部署

报道来源 [3]

1. arXiv cs.LG TIER_1 English(EN) · Chang Sun, Zhiqiang Que, Bakhtiar Zadeh, Qibin Liu, Kevin H. Alvarez, Wayne Luk, Maria Spiropulu · 2026-04-27 04:00

   HGQ-LUT: Fast LUT-Aware Training and Efficient Architectures for DNN Inference

   arXiv:2604.22293v1 Announce Type: cross Abstract: Lookup-table (LUT) based neural networks can deliver ultra-low latency and excellent hardware efficiency on FPGAs by mapping arithmetic operations directly onto the logic primitives. However, state-of-the-art LUT-aware training (L…

2. arXiv cs.LG TIER_1 English(EN) · Chang Sun, Zhiqiang Que, Vladimir Loncar, Wayne Luk, Maria Spiropulu · 2026-04-27 04:00

   da4ml: Distributed Arithmetic for Real-time Neural Networks on FPGAs

   arXiv:2507.04535v2 Announce Type: replace-cross Abstract: Neural networks with a latency requirement on the order of microseconds, like the ones used at the CERN Large Hadron Collider, are typically deployed on FPGAs fully unrolled and pipelined. A bottleneck for the deployment o…

3. arXiv cs.LG TIER_1 English(EN) · Maria Spiropulu · 2026-04-24 07:13

   HGQ-LUT: Fast LUT-Aware Training and Efficient Architectures for DNN Inference

   Lookup-table (LUT) based neural networks can deliver ultra-low latency and excellent hardware efficiency on FPGAs by mapping arithmetic operations directly onto the logic primitives. However, state-of-the-art LUT-aware training (LAT) approaches remain difficult to use in practice…