English(EN) A Resource-Efficient and Precision-Scalable FPGA Accelerator for Spiking Neural Networks Using Minifloat Arithmetic

用于脉冲神经网络的FPGA加速器采用minifloat算术

作者 PulseAugur 编辑部 · [1 个来源] · 2026-10-23 01:45

研究人员开发了一种新的脉冲神经网络（SNNs）硬件加速器架构，该架构利用参数化minifloat算术。这种设计允许可配置的精度，从而在准确性、内存和功耗之间进行权衡。FPGA实现结果表明，降低minifloat精度可显著减少资源利用率和功耗，而硬件验证案例表明，在不牺牲有竞争力的推理准确性的情况下，可以实现大幅度的精度降低。 AI

影响这项研究可能有助于在资源受限的边缘设备上更有效地部署事件驱动的AI。

排序理由这是一篇详细介绍SNNs新型硬件架构的研究论文。[lever_c_demoted from research: ic=1 ai=1.0]

在 arXiv cs.NE (Neural & Evolutionary) 阅读 →

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报道来源 [1]

arXiv cs.NE (Neural & Evolutionary) TIER_1 English(EN) · Philip C. Jose · 2026-10-23 01:45

面向脉冲神经网络的资源高效、精度可伸缩FPGA加速器，采用Minifloat算术

Spiking neural networks (SNNs) are well suited to event-driven edge intelligence, but the arithmetic complexity, memory footprint, and power consumption associated with conventional floating-point implementations can limit their deployment on resource-constrained hardware. This p…

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报道来源 [1]

面向脉冲神经网络的资源高效、精度可伸缩FPGA加速器，采用Minifloat算术

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