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English(EN) Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuits

DeepSeq3框架通过层次化图学习增强电路分析能力

研究人员开发了DeepSeq3,一个用于分析时序电路的新型层次化框架。该方法将电路抽象为两级表示,结合了细粒度子图和模拟寄存器传输结构的高层超级节点图。双图神经网络架构在两个级别上学习表示,捕获局部逻辑和全局状态转换。新颖的以状态为中心的预训练方案增强了模型对时序行为的理解,从而显著提高了可扩展性,并将有界模型检查的求解时间缩短了18%。 AI

影响 该框架为电子设计自动化任务提供了更高的可扩展性和效率,有望加速复杂数字电路的开发。

排序理由 这是一篇研究论文,详细介绍了一种新的电路分析框架和方法论。[lever_c_demoted from research: ic=1 ai=1.0]

在 arXiv cs.LG 阅读 →

AI 生成摘要 · Google Gemini · 来自 1 个来源。 我们如何撰写摘要 →

DeepSeq3框架通过层次化图学习增强电路分析能力

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这是一篇研究论文,详细介绍了一种新的电路分析框架和方法论。[lever_c_demoted from research: ic=1 ai=1.0]
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报道来源 [1]

  1. arXiv cs.LG TIER_1 English(EN) · Jingyi Zhou, Zhengyuan Shi, Jiaying Zhu, Ziyang Zheng, Qiang Xu ·

    超越扁平网表:用于可扩展时序电路分析的分层图表示学习

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