Cerebras 为其 CS-4 晶圆级系统推出了一款新的 I/O 模块，解决了片外带宽的历史瓶颈。此次升级将片外 I/O 速度提高了一倍，达到 2.4Tb/s，并包含一个可现场升级的 FPGA NIC。通过允许 Cerebras 晶圆与基于高带宽内存 (HBM) 的加速器（如 AMD 和 Trainium）进行接口，克服了大型模型和更长上下文的 44GB SRAM 限制，从而实现了异构分解推理。 AI
影响 通过克服晶圆级计算中的内存限制，支持更大的模型和更长的上下文。
排序理由 这是对现有产品 (CS-4) 和新模块的升级，而不是新颖的前沿发布或重大的行业转变。
AI 生成摘要 · Google Gemini · 来自 3 个来源。 我们如何撰写摘要 →
完整方法见我们的编辑标准。
The bigger story is what this unlocks: heterogeneous disaggregated inference. The wafer is a decode machine, and its rooflines are poor for compute-bound prefill. With the new I/O module, Cerebras can pair with HBM-based XPUs (AMD and Trainium are the announced partners) in both
CS-4 makes progress here. Off-wafer I/O doubles from 1.2Tb/s to 2.4Tb/s, since the wafer's parallel I/O scales with the 2x clock bump. On top of that sits a new Wafer I/O module: a field-upgradeable FPGA NIC that converts Cerebras's proprietary I/O to standard ethernet. That
Off-chip bandwidth has always been the weak point of wafer-scale. The WSE-3 has staggering on-wafer SRAM bandwidth, but everything slows down the moment data has to leave the wafer. That mattered because the wafer only holds 44GB of SRAM, so big models get spread across many http…