Sram
PulseAugur coverage of Sram — every cluster mentioning Sram across labs, papers, and developer communities, ranked by signal.
8 day(s) with sentiment data
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Li Auto aims for Tesla FSD V14 parity with self-developed AI chips and models
Li Auto is developing its autonomous driving capabilities to match Tesla's FSD V14, focusing on safety, efficiency, and comfort, alongside advanced features like recognizing special vehicles and traffic police signals. …
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Flash Attention Mechanics Explained: Tiled Attention in SRAM
This article delves into the mechanics of Flash Attention, a technique designed to optimize the self-attention mechanism in AI models. It explains how tiled attention, a method for processing attention computations in s…
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SRAM Supply Contradiction Questioned Amidst Logic Wafer Constraints
A conversation on X highlights a perceived contradiction regarding SRAM supply. The dialogue questions the availability of SRAM, given that the logic wafers used in its fabrication are reportedly supply-constrained. Thi…
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Qualcomm unveils near-memory AI architecture to boost performance
Qualcomm has introduced a new near-memory AI architecture called High Bandwidth Compute (HBC) designed to overcome the memory wall limitations in AI workloads. This architecture places AI accelerators directly beneath L…
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Groq LPU gains traction in AI inference, challenging GPU dominance
Groq's Language Processing Unit (LPU) is gaining traction in the AI inference market, moving beyond niche applications to become a recognized component in AI infrastructure. This shift is driven by the increasing demand…
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SNIA launches MRAM SIG to standardize interfaces and boost adoption
The Storage Networking Industry Association (SNIA) has launched a Magnetoresistive Random-Access Memory (MRAM) Special Interest Group (SIG) to foster MRAM adoption. This group aims to standardize MRAM technologies and d…
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Qualcomm launches AI data center platform, secures Meta CPU deal · 3 sources tracked
Qualcomm has unveiled a new data center roadmap and product portfolio aimed at the AI era, including the Dragonfly C1000 CPU, High Bandwidth Computing (HBC) technology, and the Dragonfly AI300 inference accelerator. The…
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Groq's custom LPU chip offers 10x memory bandwidth for faster LLM inference
Groq has developed a novel Language Processing Unit (LPU) that significantly outperforms traditional GPUs for large language model (LLM) inference. Unlike GPUs, which were designed for graphics and repurposed for AI tra…
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Ferroelectric Compute-in-Memory Enables Real-Time Forecasting
Researchers have developed FerroNDS, a novel neuromorphic system utilizing ferroelectric compute-in-memory hardware for real-time forecasting. This system integrates an integrator and an oscillator, mapped onto multi-bi…
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OpenOpt framework optimizes SRAM architecture and transistor sizing
Researchers have developed OpenOpt, an open-source framework for optimizing SRAM architecture and transistor sizing. This framework utilizes equivalent circuit models to achieve significant simulation speedups while mai…
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Cerebras explores wafer-on-wafer bonding for AI chip memory boost
Cerebras is developing a wafer-on-wafer bonding technique to enhance its AI chips, addressing the scaling limitations of SRAM. This approach involves bonding a second wafer, potentially containing additional SRAM or com…
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LAM Research event highlights chiplet tech, awards Vertical Compute
LAM Research hosted an event showcasing advancements in chiplet technologies and awarded innovators. The event featured 10 startup participants, with Vertical Compute presenting its magnetic memory technology aimed at i…
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AI memory bottleneck spurs HBM, CXL, and specialized chip innovations
The AI industry is grappling with a significant 'memory wall' bottleneck, where GPU processing power outstrips memory bandwidth and capacity. This challenge is exacerbated by the increasing demands of training large gen…
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Anthropic eyes UK startup Fractile for DRAM-less AI inference chips
Anthropic is reportedly in early discussions to acquire specialized AI inference chips from UK startup Fractile. These chips utilize an SRAM architecture, which aims to reduce the reliance on expensive DRAM memory. This…
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Tessera offers secure, near-line-rate weight streaming for edge AI accelerators
Researchers have developed Tessera, a new architecture designed to securely stream model weights to edge accelerators in Unified Memory Architecture (UMA) systems. This approach addresses the challenge of protecting pro…
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Nvidia unveils low-power chip for sub-millisecond face detection
Nvidia researchers have developed an always-on vision system capable of detecting human faces in under a millisecond. This system, integrated into a chip, consumes less than 5 milliwatts while operating at 60 frames per…