据报道，Google正在为未来的TPU开发六维环面（6D Torus），以增强互连

报道来源 [8]

1. X — SemiAnalysis TIER_1 English(EN) · SemiAnalysis_ · 2026-08-17 22:01

   To learn more about ICI networking topology, please refer to our networking model (8/8) https://t.co/kqt0IiSiFi

   To learn more about ICI networking topology, please refer to our networking model (8/8) https://t.co/kqt0IiSiFi

2. X — SemiAnalysis TIER_1 English(EN) · SemiAnalysis_ · 2026-08-17 22:01

   For a fixed chip count the diameter collapses. For a 4,096 chip cluster, the worst-case is 24 hops with a 16×16×16 3D torus, but 12 hops with a 4⁶ 6D Torus. Thi

   For a fixed chip count the diameter collapses. For a 4,096 chip cluster, the worst-case is 24 hops with a 16×16×16 3D torus, but 12 hops with a 4⁶ 6D Torus. This is not the onlye benefit as bisection bandwidth multiplies. However, this all comes at the cost of far more optics

3. X — SemiAnalysis TIER_1 English(EN) · SemiAnalysis_ · 2026-08-17 22:01

   Inside the rack, chips wire up exactly as in today's 3D torus, over short copper. Each chip's other 6 neighbors sit at the same position in the six adjacent rac

   Inside the rack, chips wire up exactly as in today's 3D torus, over short copper. Each chip's other 6 neighbors sit at the same position in the six adjacent racks, and the rack grid itself forms a second 3D torus, stitched together in optics. (6/8)

4. X — SemiAnalysis TIER_1 English(EN) · SemiAnalysis_ · 2026-08-17 22:01

   A 6D torus doesn't add diagonals, it adds three entirely new dimensions, doubling each chip's ICI links from 6 to 12. It can be visually represented by a cube o

   A 6D torus doesn't add diagonals, it adds three entirely new dimensions, doubling each chip's ICI links from 6 to 12. It can be visually represented by a cube of cubes: each small cube is a TPU, each 3D-torus block is a rack. (5/8) https://t.co/5eVR8WBOaX

5. X — SemiAnalysis TIER_1 English(EN) · SemiAnalysis_ · 2026-08-17 22:01

   In a 3D torus, each TPU talks to 6 neighbors (±X, ±Y, ±Z). Picture a cube of chips: every chip links to the ones beside it, and chips on an edge wrap around to

   In a 3D torus, each TPU talks to 6 neighbors (±X, ±Y, ±Z). Picture a cube of chips: every chip links to the ones beside it, and chips on an edge wrap around to the opposite edge. That wraparound is what makes it a torus rather than a mesh, and it's what the OCS layer provides. ht…

6. X — SemiAnalysis TIER_1 English(EN) · SemiAnalysis_ · 2026-08-17 22:01

   Recent rumors hinted that Google will likely maintain this dual track with TPUv9, with the inference-specialized chip (TPUv9i) iterating to a newer version of B

   Recent rumors hinted that Google will likely maintain this dual track with TPUv9, with the inference-specialized chip (TPUv9i) iterating to a newer version of Boardfly and the training-specialized TPU (TPUv9t) introducing an evolution of 3D Torus called 6D Torus. (3/8)

7. X — SemiAnalysis TIER_1 English(EN) · SemiAnalysis_ · 2026-08-17 22:01

   With Ironwood (TPUv7), Google kept the 3D Torus of 64-chip cubes, scaled via OCS to 9,216 interconnected chips. Earlier this year during Google Cloud Next 2026,

   With Ironwood (TPUv7), Google kept the 3D Torus of 64-chip cubes, scaled via OCS to 9,216 interconnected chips. Earlier this year during Google Cloud Next 2026, the firm unveiled TPUv8t and TPUv8i, with TPUv8i introducing a new ICI topology called Boardfly and TPUv8t sticking to …

8. X — SemiAnalysis TIER_1 English(EN) · SemiAnalysis_ · 2026-08-17 22:01

   Over the years, Google has been improving its original 2D Torus Inter-Chip-Interconnect (ICI) network topology introduced with TPUv2, later extended to a 3D Tor

   Over the years, Google has been improving its original 2D Torus Inter-Chip-Interconnect (ICI) network topology introduced with TPUv2, later extended to a 3D Torus starting with TPUv4 and v5p. (1/8)🧵 https://t.co/rtU0TkUzZw