据报道，Google正在为其Tensor Processing Unit（TPU）互连拓扑进行演进，为未来的TPUv9t等模型从三维环面（3D Torus）转向六维环面（6D Torus）。这种由SemiAnalysis详细介绍的新架构旨在减少通信跳数（hops）并提高双isection带宽，尽管它需要更多的光学器件。Google还为推理专用芯片引入了Boardfly拓扑，同时为TPUv8t等训练专用芯片保留了三维环面。 AI
影响 TPU互连的这种演进可能会显著提升未来AI模型的训练和推理性能。
排序理由 该集群详细介绍了Google TPU互连拓扑的传闻中的架构变更，这是一个技术研究和开发主题。
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To learn more about ICI networking topology, please refer to our networking model (8/8) https://t.co/kqt0IiSiFi
For a fixed chip count the diameter collapses. For a 4,096 chip cluster, the worst-case is 24 hops with a 16×16×16 3D torus, but 12 hops with a 4⁶ 6D Torus. This is not the onlye benefit as bisection bandwidth multiplies. However, this all comes at the cost of far more optics
Inside the rack, chips wire up exactly as in today's 3D torus, over short copper. Each chip's other 6 neighbors sit at the same position in the six adjacent racks, and the rack grid itself forms a second 3D torus, stitched together in optics. (6/8)
A 6D torus doesn't add diagonals, it adds three entirely new dimensions, doubling each chip's ICI links from 6 to 12. It can be visually represented by a cube of cubes: each small cube is a TPU, each 3D-torus block is a rack. (5/8) https://t.co/5eVR8WBOaX
In a 3D torus, each TPU talks to 6 neighbors (±X, ±Y, ±Z). Picture a cube of chips: every chip links to the ones beside it, and chips on an edge wrap around to the opposite edge. That wraparound is what makes it a torus rather than a mesh, and it's what the OCS layer provides. ht…
Recent rumors hinted that Google will likely maintain this dual track with TPUv9, with the inference-specialized chip (TPUv9i) iterating to a newer version of Boardfly and the training-specialized TPU (TPUv9t) introducing an evolution of 3D Torus called 6D Torus. (3/8)
With Ironwood (TPUv7), Google kept the 3D Torus of 64-chip cubes, scaled via OCS to 9,216 interconnected chips. Earlier this year during Google Cloud Next 2026, the firm unveiled TPUv8t and TPUv8i, with TPUv8i introducing a new ICI topology called Boardfly and TPUv8t sticking to …
Over the years, Google has been improving its original 2D Torus Inter-Chip-Interconnect (ICI) network topology introduced with TPUv2, later extended to a 3D Torus starting with TPUv4 and v5p. (1/8)🧵 https://t.co/rtU0TkUzZw