English(EN) CascadeLUT: Information-Ordered Streaming Inference for Bandwidth-Constrained FPGAs

CascadeLUT 优化FPGA神经网络推理以应对带宽限制

作者 PulseAugur 编辑部 · [1 个来源] · 2026-08-04 04:00

研究人员开发了CascadeLUT，一个用于在带宽受限条件下优化现场可编程门阵列（FPGA）上神经网络推理的新颖框架。该方法将特征划分为有序子集，允许在数据到达时逐步细化预测，从而减少数据移动并提高吞吐量。与现有的基于查找表（LUT）的方法相比，CascadeLUT在延迟、吞吐量和能耗方面均有显著改善，同时还集成了片上输入量化以获得进一步的效率提升。 AI

影响这项研究可能导致在带宽有限的边缘设备上实现更高效的AI推理。

排序理由详细介绍新技术方法的学术论文。[lever_c_demoted from research: ic=1 ai=1.0]

在 arXiv cs.LG 阅读 →

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报道来源 [1]

arXiv cs.LG TIER_1 English(EN) · Oliver Cassidy, Marta Andronic, George A. Constantinides · 2026-08-04 04:00

CascadeLUT：面向带宽受限FPGA的信息有序流式推理

arXiv:2608.00720v1 Announce Type: cross Abstract: Mapping neural networks to FPGAs enables low-latency, energy-efficient inference, particularly for lookup table (LUT)-based models that eliminate multipliers and map directly to reconfigurable fabric. While prior work achieves hig…

本文如何被排名

报道来源 [1]

CascadeLUT：面向带宽受限FPGA的信息有序流式推理

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