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English(EN) SMIC's third-gen 7nm node shows smaller metal pitch than Intel 18A, higher transistor density than TSMC N6 without EUV — analysis of N+3 shows significant advancement for Chinese semi manufacturing

中芯国际7纳米制程在无EUV情况下取得进展,但性能落后

中芯国际的第三代7纳米级(N+3)制造技术实现了比Intel 18A更小的金属间距,以及比台积电N6更高的晶体管密度,并且显著地未使用EUV光刻技术。这代表了中国半导体制造的重大进展,采用了DUV多重曝光和设计-工艺协同优化等技术。然而,N+3工艺的晶体管密度并未转化为整体竞争力,其生产的芯片在性能和能效方面与大约三年前的旗舰处理器相当,落后于主要竞争对手的现代设计。 AI

影响 这项制造技术的进步最终可能影响AI芯片的成本和性能,尽管目前的能效仍有差距。

排序理由 对中国主要制造商的一款新型半导体制造节点的分析,详细介绍了其技术规格和竞争定位。

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中芯国际7纳米制程在无EUV情况下取得进展,但性能落后

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对中国主要制造商的一款新型半导体制造节点的分析,详细介绍了其技术规格和竞争定位。
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报道来源 [2]

  1. Tom's Hardware TIER_1 English(EN) · Anton Shilov ·

    中芯国际第三代7纳米制程金属间距小于Intel 18A,晶体管密度高于台积电N6(无EUV)——N+3分析显示中国半导体制造取得重大进展

    SMIC's N+3 process technology can achieve transistor density comparable to TSMC's N6 without using EUV lithography, but it fails to deliver performance or efficiency of modern production nodes.

  2. Mastodon — mastodon.social TIER_1 English(EN) · [email protected] ·

    中芯国际第三代7nm工艺金属间距小于Intel 18A,晶体管密度高于台积电N6(无EUV)——对中芯国际N+3工艺技术的分析

    SMIC's third-gen 7nm node shows smaller metal pitch than Intel 18A, higher transistor density than TSMC N6 without EUV — analysis of… SMIC's N+3 process technology can achieve transistor density comparable to TSMC's N6 without using EUV lithography, but it fails to deliver perfor…