LLM agents design RISC-V CPUs with FPGA evaluation, speeding up development

Researchers have developed a new environment for designing RISC-V CPUs using LLM agents and FPGA-in-the-loop evaluation. This approach significantly speeds up the design and decision-making process compared to traditional RTL simulation. The system was used to develop a single-cycle RV32I core into a three-wide out-of-order RV32IM core, which achieved 5.61 CoreMark/MHz at 130 MHz on an Artix-7 FPGA. This FPGA evaluation was 9.6x faster than RTL simulation for an 8,000 CoreMark iteration run and successfully identified performance degradation missed by shorter diagnostic tests. AI

IMPACT Accelerates hardware design cycles by leveraging LLMs and FPGAs for rapid prototyping and evaluation.

RANK_REASON Academic paper detailing a novel methodology for CPU design. [lever_c_demoted from research: ic=1 ai=1.0]

Read on arXiv cs.AI →

• Artix-7
• arXiv
• Coremark
• field-programmable gate array
• LLM
• RISC-V
• RTL
• RV32I
• RV32IM

• paper
• infra

AI-generated summary · Google Gemini · from 1 sources. How we write summaries →