field-programmable gate array
PulseAugur coverage of field-programmable gate array — every cluster mentioning field-programmable gate array across labs, papers, and developer communities, ranked by signal.
- used by Spiking neural networks 90%
- used by CNN 80%
- competes with graphics processing unit 70%
- developed Spiking neural networks 70%
- used by hls4ml 70%
- used by Large Hadron Collider 70%
- instance of CNN 70%
- developed by Spiking neural networks 70%
- used by application-specific integrated circuit 70%
- instance of application-specific integrated circuit 60%
- used by central processing unit 60%
- competes with application-specific integrated circuit 50%
11 day(s) with sentiment data
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FPGA accelerator boosts U-Net energy efficiency with merged arithmetic · 3 sources tracked
Researchers have developed an energy-efficient hardware accelerator for U-Net's convolutional layers, implemented on a field-programmable gate array (FPGA). The proposed merged multiply-add (MMA) architecture fuses oper…
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PatchINR reduces INR inference latency by 75% using patch-based approach
Researchers have developed PatchINR, a novel patch-based approach to Implicit Neural Representations (INRs) that significantly reduces computational costs for high-resolution signal modeling. By processing non-overlappi…
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New memristive synapse design promises highly efficient on-chip neural networks
Researchers have developed a physics-based design for an on-chip neural network utilizing multi-level memristive synapses capable of supporting a wide range of conductance states. This design, rooted in ionic transport …
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FPGA-accelerated system achieves 97% accuracy for orbital object detection
Researchers have developed an FPGA-accelerated neuromorphic vision system for real-time detection of resident space objects (RSOs). This open-source framework adapts a grid clustering algorithm for FPGA acceleration, in…
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NeuronFabric architecture enables on-chip transformer training
Researchers have introduced NeuronFabric, a software reference architecture designed for on-chip transformer training using local Adam updates. A C# prototype demonstrates the feasibility of this approach, handling forw…
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Survey explores FPGA-based neural network accelerators for space missions
A survey paper published on arXiv explores the use of Field-Programmable Gate Arrays (FPGAs) for accelerating neural networks in space applications. The paper highlights the growing need for advanced onboard computing i…
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New VQ4SNN architecture boosts memory efficiency for FPGA Spiking Neural Networks
Researchers have developed VQ4SNN, a novel architecture designed to make Spiking Neural Networks (SNNs) more memory-efficient for deployment on FPGAs. This approach utilizes Vector Quantization (VQ) to reduce the signif…
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New research advances Spiking Neural Networks for efficiency and verification
Researchers have developed novel methods for Spiking Neural Networks (SNNs), focusing on improving their efficiency and verification capabilities. One study introduces a learnable residual speech-to-spike encoder that e…
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KANs accelerate machine learning on FPGAs for ultrafast inference
Researchers have developed a novel approach to accelerate machine learning on Field-Programmable Gate Arrays (FPGAs) using Kolmogorov-Arnold Networks (KANs). This method aims to achieve ultrafast inference and online le…
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LLMs automate FPGA accelerator design for AI workloads
Researchers have developed SECDA-DSE, a framework that integrates Large Language Models (LLMs) to automate the design of FPGA-based accelerators for AI workloads. This system uses LLMs for reasoning-guided exploration, …
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hls4ml extended for Spiking Neural Network deployment on FPGAs
Researchers have developed an extension for the hls4ml toolkit to enable the deployment of Spiking Neural Networks (SNNs) on Field-Programmable Gate Arrays (FPGAs). This new capability allows for clock-driven inference …
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SNAC-Pack automates neural architecture search for FPGAs
Researchers have developed SNAC-Pack, an open-source framework designed to automate the process of neural architecture search (NAS) specifically for FPGAs. This package addresses the limitations of existing NAS methods …
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New ITP-STDP engine slashes SNN training energy use
Researchers have developed a new learning engine called ITP-STDP for training spiking neural networks (SNNs) that significantly reduces hardware resource utilization and energy consumption. This novel approach optimizes…
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New FPGA engine TRINE accelerates multimodal AI inference
Researchers have developed TRINE, a novel FPGA accelerator designed for efficient multimodal AI inference. This system unifies various AI model architectures, including ViTs, CNNs, GNNs, and transformers, into a single,…
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New FPGA-based motion estimation for event-based vision sensors
Researchers have developed EventShiftFlow, a novel method for hardware-efficient motion estimation using event-based vision sensors. This approach discretizes asynchronous events into time bins and utilizes simple integ…
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New SNAC-Pack automates neural architecture co-design for FPGAs
Researchers have developed SNAC-Pack, an open-source framework designed to automate the co-design of neural architectures and their deployment on FPGAs. This package employs a multi-objective global search strategy comb…
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Neuromorphic computing achieved with autonomous spiking dynamics on FPGAs
Researchers have developed a scalable neuromorphic computing architecture that utilizes autonomous spiking dynamics within clockless digital circuits. Implemented on FPGAs, this system features configurable networks of …
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Open-source SNN accelerator integrated into FPGA-based neuromorphic SoC
Researchers have developed a heterogeneous System-on-Chip (SoC) that integrates an open-source Recurrent Spiking Neural Network (SNN) accelerator called ReckOn. This design aims to bring efficient, low-power neuromorphi…
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FPGA accelerators boost energy efficiency for Spiking Neural Networks
Two new research papers detail advancements in energy-efficient Spiking Neural Networks (SNNs) implemented on Field-Programmable Gate Arrays (FPGAs). The first paper introduces SPIKER-LL, an FPGA accelerator designed fo…
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LLMs automate FPGA accelerator design space exploration with SECDA-DSE framework
Researchers have developed SECDA-DSE, a new framework that leverages Large Language Models (LLMs) to automate the design space exploration of FPGA-based accelerators. This system integrates LLMs with existing SECDA tool…