field-programmable gate array
PulseAugur coverage of field-programmable gate array — every cluster mentioning field-programmable gate array across labs, papers, and developer communities, ranked by signal.
- used by Spiking neural networks 90%
- used by CNN 90%
- developed Spiking neural networks 70%
- used by application-specific integrated circuit 70%
- developed by CNN 70%
- instance of application-specific integrated circuit 70%
- used by central processing unit 70%
- developed by Spiking neural networks 70%
- used by Large Hadron Collider 70%
- used by hls4ml 70%
- instance of CNN 70%
- competes with application-specific integrated circuit 50%
7 day(s) with sentiment data
-
HLSmith framework boosts C/C++ to HLS translation with expert guidance · 2 sources tracked
Researchers have developed HLSmith, a framework designed to improve the translation of C/C++ code into high-performance hardware accelerators using High-Level Synthesis (HLS). The system incorporates an expertise librar…
-
CascadeLUT optimizes FPGA neural network inference for bandwidth limits
Researchers have developed CascadeLUT, a novel framework for optimizing neural network inference on field-programmable gate arrays (FPGAs) under bandwidth constraints. This approach partitions features into ordered subs…
-
New hls4ml backend enables ML on radiation-hard FPGAs for physics experiments
Researchers have developed a new backend for the hls4ml tool, enabling the use of machine learning models on radiation-hard FPGAs. This advancement is demonstrated through a lightweight autoencoder designed for the Pico…
-
New KAN Compression and Binary KAN Restoration Techniques Unveiled
Researchers have developed SparseKAN, a method to compress Kolmogorov-Arnold Networks (KANs) by reducing basis functions, neurons, and numerical precision. This approach aims to make KANs more efficient by removing redu…
-
Transformer Neural Networks Optimized for Real-Time Outlier Detection on FPGAs
Researchers have developed a method to optimize Transformer Neural Networks for real-time outlier detection in financial time series data. This approach leverages the capabilities of Field-Programmable Gate Arrays (FPGA…
-
FPGA recreates F-14 Tomcat's 'first microprocessor' in 3D-printed model
An FPGA recreation of the Central Air Data Computer (CADC) from the Grumman F-14 Tomcat has been developed and demonstrated in a 3D-printed scale model. This recreation focuses on the MP944 chip, which some experts argu…
-
Developer Denies AI Involvement in Midway Wolf Unit FPGA Core
A developer has denied claims that their work on an FPGA core for Midway's Wolf Unit arcade board involved artificial intelligence. The developer, known as blahm1d, stated that the assertion was a complete fabrication. …
-
New E-SpecFormer model offers efficient RF spectrum monitoring for IoT
Researchers have developed E-SpecFormer, a new Transformer model designed for efficient RF spectrum monitoring on edge devices. This model incorporates a novel attention mechanism called LiTAN, which reduces computation…
-
New FPGA Architecture Boosts ML Inference Efficiency
Researchers have developed a novel FPGA architecture called NIFA that enhances deep learning inference efficiency. This architecture integrates an ADC-free In-Memory Computing (IMC) block using analog content-addressabl…
-
Machine learning enhances data reconstruction for silicon sensors in high energy physics
Researchers have developed machine learning techniques to improve data reconstruction and compression for resistive silicon sensors used in high energy physics. The study explores recurrent neural networks, specifically…
-
Peking University achieves 100x AI speed boost with optical chip breakthrough
Researchers at Peking University have developed a novel all-optical interconnect system that significantly enhances AI processing speed. This breakthrough utilizes optical signals to link standard electronic chips, achi…
-
New pruning technique optimizes GCNs for embedded event-based vision
Researchers have developed a hardware-aware pruning and quantization strategy for Graph Convolutional Neural Networks (GCNs) designed for embedded event-based vision systems. This method aims to optimize GCN models for …
-
BitLogic framework unifies training for FPGA-native neural networks
Researchers have developed BitLogic, a unified framework designed to standardize the training and evaluation of gradient-based neural networks that utilize Boolean logic operations instead of traditional multiply-accumu…
-
DBNN enables accurate, low-power neural spike sorting for brain-computer interfaces
Researchers have developed a Deep Binarized Neural Network (DBNN) for on-node spike sorting in implantable brain-computer interfaces. This DBNN system, featuring two binarized hidden layers, enables multiplier-free infe…
-
New Transformer Architecture for FPGAs Achieves High Compression
Researchers have developed ELiTeFormer, a novel Transformer model architecture specifically designed for efficient deployment on field-programmable gate arrays (FPGAs). This architecture unifies hybrid linear attention …
-
New research enables fine-grained computation offload in servers
A new research paper proposes a method for fine-grained computation offload in servers, aiming to improve performance by overlapping offloads with other requests. The approach leverages existing concurrency mechanisms w…
-
AI-Generated FPGA Cores Face Scrutiny Over Accuracy Concerns
A recent article questions the accuracy and future viability of AI-generated field-programmable gate array (FPGA) cores. The author expresses significant disappointment, suggesting that while AI may offer a path forward…
-
New hardware architecture enforces semantic coordination for autonomous systems
Researchers have developed a novel hardware-enforced semantic coordination architecture to enhance the safety and real-time performance of complex autonomous systems. This approach utilizes field-programmable gate array…
-
New framework enhances fault tolerance in FPGA-based CNN accelerators
Researchers have developed ProWAFT, a novel fault-tolerance framework designed for CNN accelerators implemented on SRAM-based FPGAs. This system addresses the challenge of transient faults that can compromise reliabilit…
-
FlexViT: FPGA Accelerator Boosts Edge Vision Transformer Performance
Researchers have developed FlexViT, a flexible FPGA-based accelerator designed to improve the efficiency of Vision Transformer (ViT) models on edge devices. This accelerator addresses the challenges posed by the heterog…