field-programmable gate array
PulseAugur coverage of field-programmable gate array — every cluster mentioning field-programmable gate array across labs, papers, and developer communities, ranked by signal.
- used by hls4ml 80%
- developed by hls4ml 70%
- developed Spiking neural networks 70%
- instance of application-specific integrated circuit 70%
- developed by CNN 70%
- used by CNN 70%
- instance of CNN 70%
- used by Spiking neural networks 70%
- used by Large Hadron Collider 70%
- developed hls4ml 70%
- used by application-specific integrated circuit 70%
- used by central processing unit 60%
12 day(s) with sentiment data
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MeshKV architecture boosts transformer decoding with novel NoC KV cache fabric
Researchers have developed MeshKV, a novel network-on-chip (NoC) architecture designed to accelerate transformer decoding by optimizing the movement of key-value (KV) caches. This system addresses bottlenecks in traditi…
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FPGA platform accelerates approximate multiplier evaluation for DNNs
Researchers have developed FAME, a new platform utilizing FPGAs to accelerate the evaluation of approximate multipliers for deep neural networks. This hardware-based approach significantly reduces the time needed to ass…
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WARD framework enhances edge AI Vision Transformers with adaptive reliability
Researchers have developed WARD, a novel framework designed to enhance the dependability of Vision Transformers used in edge AI applications. WARD addresses the challenges of dynamic power budgets, changing reliability …
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New framework optimizes AI model compression for FPGA deployment
Researchers have developed FairCompressAgent (FCA), a new framework designed to optimize model compression for deployment on field-programmable gate arrays (FPGAs). FCA integrates various compression techniques like pru…
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FPGA-accelerated Broad Learning framework improves harmonic analysis for EV charging
Researchers have developed an Efficient Broad Learning (EBL) framework designed to accelerate harmonic analysis in power grids, particularly for managing distortions caused by electric vehicles. This FPGA-accelerated ap…
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SkyEgg framework optimizes FPGA hardware synthesis with algebraic rules
Researchers have developed SkyEgg, a new hardware synthesis framework designed to better exploit the heterogeneity of modern field-programmable gate arrays (FPGAs). Unlike previous frameworks that treated resources sequ…
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Syn2Logic framework automates neuromorphic hardware design
Researchers have developed Syn2Logic, a novel framework for end-to-end neuromorphic design automation (eNDA). This system allows neuroscientists to model neural behavior using a custom domain-specific language, which is…
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New OASIS framework slashes in-sensor vision data transmission costs
Researchers have developed OASIS, a novel framework for distributed in-sensor vision that significantly reduces data transmission costs by processing information near the image sensor. This system employs a lightweight …
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Biologically-inspired neural network runs on memristor hardware
Researchers have developed a novel spiking neural network inspired by the rodent CA3 hippocampal subregion, demonstrating its functionality on memristor hardware. This network incorporates neuronal diversity and realist…
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New BiHDTrans model merges hyperdimensional computing with Transformers for efficient time series classification
Researchers have developed BiHDTrans, a novel neurosymbolic binary hyperdimensional Transformer designed for efficient multivariate time series classification, particularly for resource-constrained edge environments. Th…
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New method trains neural networks directly on FPGAs
Researchers have developed DiffLUT-Net, a novel approach for training neural networks directly on field-programmable gate arrays (FPGAs). This method enables the learning of both the truth-table entries for lookup table…
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FPGA emulator core achieves 99% speed for Sega's Virtua Racing
A new emulator core has been developed for field-programmable gate arrays (FPGAs) that accurately replicates the Sega Model 1 hardware, enabling the game Virtua Racing to run at approximately 99% of its original speed. …
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New T-KAN architecture boosts high-frequency trading forecasts
Researchers have introduced Temporal Kolmogorov-Arnold Networks (T-KAN), a novel architecture designed to improve high-frequency trading (HFT) forecasting. Unlike traditional models that struggle with noisy, non-linear …
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SymbolicLight V2 achieves 27.6% energy reduction for language inference
Researchers have developed SymbolicLight V2, a hybrid neuromorphic architecture designed for low-energy language inference. This updated model enhances its predecessor, SymbolicLight V1, by incorporating graded signed e…
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AI-friendly motors prioritize good interface design for AI control
The term "AI-friendly" for motors is being redefined to emphasize engineering properties that benefit both human programmers and AI models. Key attributes include intent-level commands rather than low-level timing, clea…
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New TriCCOT Architecture Enables Onboard Space Object Detection on FPGAs
Researchers have developed TriCCOT, a novel architecture designed for onboard object detection in space observation missions. This system addresses the limitations of computational resources and imperfect imagery by com…
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Survey details Transformer inference deployment on FPGA platforms
A recent survey paper published on arXiv details the advancements in deploying Transformer inference on Field Programmable Gate Array (FPGA) platforms. The paper highlights FPGAs as a promising alternative to traditiona…
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Neuromorphic speech recognition achieves 99.77% accuracy using novel spike encoding
Researchers have developed a novel method for efficient neuromorphic speech recognition by encoding audio data into spikes for processing by Spiking Neural Networks (SNNs). This approach aims to reduce the energy consum…
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FPGAs emerge as key to AI-era data infrastructure, overcoming ASIC limitations
The rapid advancement of AI and converging technologies necessitates a more agile data infrastructure than traditional Application-Specific Integrated Circuits (ASICs) can provide. ASICs, while efficient, suffer from lo…
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AI Chip Architectures: GPUs, TPUs, NPUs, and FPGAs Explained
The article breaks down the distinct roles of various AI accelerators, explaining that GPUs excel at massive parallelism, TPUs are optimized for matrix operations, and NPUs and FPGAs are designed for efficiency and spec…