field-programmable gate array
PulseAugur coverage of field-programmable gate array — every cluster mentioning field-programmable gate array across labs, papers, and developer communities, ranked by signal.
- used by Spiking neural networks 90%
- used by lookup table 90%
- used by hls4ml 80%
- developed by Spiking neural networks 70%
- developed Spiking neural networks 70%
- developed by hls4ml 70%
- instance of lookup table 70%
- used by CNN 70%
- instance of CNN 70%
- used by central processing unit 70%
- used by Large Hadron Collider 70%
- developed hls4ml 70%
15 day(s) with sentiment data
-
Silinx offers browser-based FPGA design platform for education
A new open-source platform called Silinx has been developed to provide a browser-based alternative for teaching digital systems design on FPGA boards. This platform aims to overcome the challenges of using outdated vend…
-
New toolchain enables ML model development on AWS cloud FPGAs
Researchers have developed a new toolchain to facilitate the development of machine learning models on AWS cloud FPGA infrastructure using high-level languages. This system bridges Vitis HLS to the AFI workflow, address…
-
Engineer builds FPGA Game Boy console with cartridge ripping and HDMI
Electronics engineer Thomas Sanfourche has developed the SGBC, a new console that uses field-programmable gate array (FPGA) technology to natively play original Game Boy cartridges. The device features HDMI output, USB-…
-
Optical AI advancements aim to boost data center efficiency and cut power use
Two distinct approaches to improving AI data center efficiency are being explored. One, Halley, is a predictive control plane for optical AI data center networks that forecasts failures and manages resources to increase…
-
Ex-Microsoft engineer builds custom RAM for vintage PDP-11 using AI
A former Microsoft engineer, Dave Plummer, has successfully built a custom RAM board for a vintage 1970s PDP-11 computer. Faced with exorbitant prices for original memory modules, Plummer utilized AI tools like ChatGPT …
-
LLM agents design RISC-V CPUs with FPGA evaluation, speeding up development
Researchers have developed a new environment for designing RISC-V CPUs using LLM agents and FPGA-in-the-loop evaluation. This approach significantly speeds up the design and decision-making process compared to tradition…
-
Audiophile network hub priced at $4,700 offers no sonic benefit, experts say
Aurender has released the NH10 Network Hub, a high-end network switch designed for audiophiles, priced at $4,700. The device features eight gigabit ports, with four copper ports incorporating seven electrical filtering …
-
SpikeAD: Multiplication-Free Neuromorphic Architecture for Energy-Efficient Object Detection
Researchers have developed SpikeAD, a novel neuromorphic architecture designed for energy-efficient small object detection in aerial platforms. This architecture utilizes spiking neural networks (SNNs) with a unique app…
-
FPGA Speech Enhancer Achieves Efficiency Gains with Low-Precision Storage and Sparse Execution
Researchers have developed a novel approach to optimize speech enhancement accelerators on field-programmable gate arrays (FPGAs) by focusing on low-precision storage and sparse execution. Their method, implemented on t…
-
Fruit-fly brain connectome simulated on single FPGA
Researchers have developed FPGAFly, a system capable of simulating the entire 166.7k-neuron fruit-fly (Drosophila) central nervous system on a single field-programmable gate array (FPGA). This was achieved through novel…
-
Survey details Vision Transformer compression for edge devices
A new survey paper published on arXiv details strategies for compressing and accelerating Vision Transformers (ViTs) for deployment on edge devices. The paper systematically reviews various model compression techniques …
-
New research explores watermarking for hyperdimensional computing classifiers
Researchers have investigated model watermarking techniques for hyperdimensional computing (HDC) classifiers, adapting backdoor-based embedding to three distinct HDC models. The study found that error-driven classifiers…
-
FPGA accelerator for Spiking Neural Networks uses minifloat arithmetic
Researchers have developed a new hardware accelerator architecture for Spiking Neural Networks (SNNs) that utilizes parameterized minifloat arithmetic. This design allows for configurable precision, enabling a trade-off…
-
New continuous-state probabilistic computer hardware demonstrated
Researchers have demonstrated a novel continuous-state probabilistic computer (CPC) that utilizes programmable energy-defined sampling for complex problem-solving. Unlike traditional binary systems, this CPC handles con…
-
Survey maps reinforcement learning implementations on FPGAs and ICs
This survey paper reviews over 100 studies on the implementation of reinforcement learning (RL) algorithms on field-programmable gate arrays (FPGAs) and integrated circuits (ICs). It categorizes research by RL algorithm…
-
New LEAF attention mechanism optimizes transformers for FPGAs
Researchers have developed LEAF, a novel LUT-aware efficient attention mechanism designed for FPGAs. This approach addresses the challenge of deploying large, high-performing transformers on FPGAs for real-time systems …
-
Survey maps reinforcement learning implementations on FPGAs and ICs
This survey examines over 100 studies on the implementation of reinforcement learning (RL) algorithms on field-programmable gate arrays (FPGAs) and integrated circuits (ICs). It categorizes research by RL family, hardwa…
-
Spiking MoveNet architecture shows promise for satellite pose estimation
Researchers have evaluated a spiking version of the MoveNet architecture, named S-MoveNet-Lightning, for pose estimation in autonomous spacecraft. This spiking neural network (SNN) approach aims to leverage energy effic…
-
FPGA-based Spiking Neural Network enables on-chip training and classification
Researchers have developed a novel FPGA-based Spiking Neural Network (SNN) designed for efficient spatiotemporal pattern recognition and on-device adaptation. This implementation supports both inference and training dir…
-
LLM-Assisted Framework Improves FPGA Timing Closure
Researchers have developed LATCH, a framework that uses Large Language Models (LLMs) to assist in the timing closure of post-route Field-Programmable Gate Arrays (FPGAs). The study compared different levels of LLM contr…