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Intel patents XBM memory architecture to cut AI chip costs

By PulseAugur Editorial · [5 sources] ·

Intel has patented a new memory architecture called XBM (Cross-Batch Memory) designed to reduce the cost and complexity of AI memory systems. XBM aims to bypass the need for expensive silicon interposers used in High Bandwidth Memory (HBM) by employing backend-transistor DRAM and UCIe interconnects. This approach could alleviate the "memory wall" bottleneck in AI chips by offering improved scalability and built-in repair mechanisms to enhance yield. AI

IMPACT Could reduce AI chip manufacturing costs and improve memory performance.

RANK_REASON Patent application for a new memory architecture.

Read on Mastodon — fosstodon.org →

AI-generated summary · Google Gemini · from 5 sources. How we write summaries →

Intel patents XBM memory architecture to cut AI chip costs

COVERAGE [5]

  1. 36氪 (36Kr) TIER_1 中文(ZH) ·

    Intel patent reveals new XBM memory architecture, aiming to bypass HBM silicon interposers to reduce AI memory costs

    7月8日消息，英特尔一项近日公开的专利申请显示，公司正研发名为XBM（Cross-Batch Memory）的新型高带宽内存架构，旨在通过取消HBM所需的硅中介层、采用UCIe互连及内置冗余修复机制，降低先进封装成本并缓解AI芯片“内存墙”瓶颈。专利显示，XBM采用后端晶体管（BEOL）DRAM堆叠设计，可在保持与HBM4相近封装尺寸的同时提升可扩展性，并支持缺陷修复以提高良率。（界面）

  2. Tom's Hardware TIER_1 English(EN) · Etiido Uko ·

    Researchers turn HBM on its side to tackle AI memory’s heat wall — Korean V-Die and Japanese MOSAIC designs promise higher bandwidth, denser stacks, and cooler future GPUs

    Researchers in Korea and Japan have proposed sideways-stacked DRAM designs that could push future AI memory beyond conventional HBM limits by improving cooling, bandwidth, and capacity while reducing reliance on TSV-heavy vertical stacks.

  3. Tom's Hardware TIER_1 English(EN) · Etiido Uko ·

    Intel patent reveals new XBM memory architecture that ditches HBM's costly silicon interposer — backend-transistor DRAM stack uses UCIe links and built-in repair to ease AI's memory bottleneck

    Intel’s XBM patent proposes an HBM alternative that uses backend-transistor DRAM, UCIe chiplet links, and repair logic to reduce packaging costs and complexity.

  4. Mastodon — fosstodon.org TIER_1 English(EN) · [email protected] ·

    Researchers turn HBM on its side to tackle AI memory’s heat wall — Korean V-Die and Japanese MOSAIC desig… Researchers in Korea and Japan have proposed sideways

    Researchers turn HBM on its side to tackle AI memory’s heat wall — Korean V-Die and Japanese MOSAIC desig… Researchers in Korea and Japan have proposed sideways-stacked DRAM designs that could push future AI memory beyond conventional HBM limits by improving cooling, bandwidth, a…

    LINKS tomshardware.com/…/researchers-turn-hbm-o… tomshardware.com/tech-industry
  5. Mastodon — fosstodon.org TIER_1 English(EN) · [email protected] ·

    Intel patent reveals new XBM memory architecture that ditches HBM's costly silicon interposer — backend-transistor DRAM stack uses UCIe links and built-in repai

    Intel patent reveals new XBM memory architecture that ditches HBM's costly silicon interposer — backend-transistor DRAM stack uses UCIe links and built-in repair to … Intel’s XBM patent proposes an HBM alternative that uses backend-transistor DRAM, UCIe chiplet links, and repair …

    LINKS tomshardware.com/…/intel-patent-reveals-n… tomshardware.com/tech-industry

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