UCIe
PulseAugur coverage of UCIe — every cluster mentioning UCIe across labs, papers, and developer communities, ranked by signal.
-
Arm launches Neoverse CSS N4 'Ranger' platform with up to 128 cores
Arm Holdings has launched its new Neoverse CSS N4 platform, codenamed Ranger, which supports up to 128 cores per die and is built on TSMC's N3P process. This semi-custom program allows clients to configure Arm's IP for …
-
Oxmiq Labs proposes High Bandwidth Flash for AI inference capacity
Oxmiq Labs is proposing High Bandwidth Flash (HBF) as a new capacity tier for AI inference, aiming to offer significantly more storage at a comparable cost to High Bandwidth Memory (HBM). Their presentation at Hot Chips…
-
Arm details AGI server CPU with dual-chiplet design for AI workloads
Arm has detailed its upcoming AGI server CPU, slated for release in late 2026. This processor features a dual-chiplet design, with each chiplet containing 70 Neoverse V3 cores and utilizing TSMC's N3P technology. A key …
-
Intel integrates UCIe in budget Wildcat Lake chips using 18A process
Intel has detailed its upcoming Wildcat Lake processors, which will feature the Universal Chiplet Interconnect Express (UCIe) standard. Despite being a value-focused chip, Wildcat Lake incorporates Intel's latest 18A pr…
-
Synopsys validates first 3D PCIe 6.0 PHY in stacked chip design
Synopsys has developed and validated the first 3D PCIe 6.0 test chip, integrating a PHY within a face-to-face stacked package. This chip achieves 64 GT/s per lane and uses PAM4 signaling, meeting the standard's bit erro…
-
SK Hynix, SanDisk unveil High Bandwidth Flash for AI inference memory wall
SK Hynix and SanDisk have collaborated to develop High Bandwidth Flash (HBF), a new memory tier designed to address the memory wall challenges in AI inference. HBF places large-capacity NAND flash memory close to variou…
-
SanDisk, SK Hynix unveil High Bandwidth Flash spec for AI memory
SanDisk and SK Hynix have jointly introduced the High Bandwidth Flash (HBF) specification, a new open standard designed to enhance memory capacity and bandwidth for AI inference systems. This technology aims to bridge t…
-
TYLsemi emerges with $43M to simplify custom AI chiplet development
TYLsemi, a new semiconductor firm, has emerged from stealth with $43 million in early-stage funding. The company aims to simplify the development of custom processors, particularly for AI infrastructure, by offering reu…
-
Intel patents XBM memory architecture to cut AI chip costs
Intel has patented a new memory architecture called XBM (Cross-Batch Memory) designed to reduce the cost and complexity of AI memory systems. XBM aims to bypass the need for expensive silicon interposers used in High Ba…