UCIe
PulseAugur coverage of UCIe — every cluster mentioning UCIe across labs, papers, and developer communities, ranked by signal.
3 day(s) with sentiment data
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Synopsys validates first 3D PCIe 6.0 PHY in stacked chip design
Synopsys has developed and validated the first 3D PCIe 6.0 test chip, integrating a PHY within a face-to-face stacked package. This chip achieves 64 GT/s per lane and uses PAM4 signaling, meeting the standard's bit erro…
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SK Hynix, SanDisk unveil High Bandwidth Flash for AI inference memory wall
SK Hynix and SanDisk have collaborated to develop High Bandwidth Flash (HBF), a new memory tier designed to address the memory wall challenges in AI inference. HBF places large-capacity NAND flash memory close to variou…
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SanDisk, SK Hynix unveil High Bandwidth Flash spec for AI memory
SanDisk and SK Hynix have jointly introduced the High Bandwidth Flash (HBF) specification, a new open standard designed to enhance memory capacity and bandwidth for AI inference systems. This technology aims to bridge t…
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TYLsemi emerges with $43M to simplify custom AI chiplet development
TYLsemi, a new semiconductor firm, has emerged from stealth with $43 million in early-stage funding. The company aims to simplify the development of custom processors, particularly for AI infrastructure, by offering reu…
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Intel patents XBM memory architecture to cut AI chip costs
Intel has patented a new memory architecture called XBM (Cross-Batch Memory) designed to reduce the cost and complexity of AI memory systems. XBM aims to bypass the need for expensive silicon interposers used in High Ba…