Synopsys validates first 3D PCIe 6.0 PHY in stacked chip design

By PulseAugur Editorial · [1 sources] · 2026-08-20 13:32

Synopsys has developed and validated the first 3D PCIe 6.0 test chip, integrating a PHY within a face-to-face stacked package. This chip achieves 64 GT/s per lane and uses PAM4 signaling, meeting the standard's bit error rate requirements. The development involved adapting an existing 2D chip design by adding through-silicon vias and redesigning circuits for 3D packaging, which presents unique challenges for signal routing and integrity. AI

IMPACT This advancement in high-speed interconnects for stacked chips could enable more powerful AI hardware by improving data transfer rates.

RANK_REASON The item details a technical validation and publication of a new chip design methodology for advanced packaging. [lever_c_demoted from research: ic=1 ai=0.7]

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Synopsys validates first 3D PCIe 6.0 PHY in stacked chip design

COVERAGE [1]

Tom's Hardware TIER_1 English(EN) · Luke James · 2026-08-20 13:32

Synopsys validates a PCIe 6.0 PHY inside a face-to-face 3D stack at 64 GT/s — says it got there by pulling apart an existing 2D test chip

Synopsys has published silicon results for what it calls the first 3D PCIe 6.0 test chip, a 5nm PHY built into a face-to-face stacked package.

COVERAGE [1]

Synopsys validates a PCIe 6.0 PHY inside a face-to-face 3D stack at 64 GT/s — says it got there by pulling apart an existing 2D test chip

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