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English(EN) VeriHGN: Heterogeneous Graph-Based Congestion Prediction for Chip Layout Verification

新的VeriHGN框架预测芯片布局拥塞

作者 PulseAugur 编辑部 · [1 个来源] ·

研究人员开发了VeriHGN，一个用于芯片布局验证中预测拥塞的新框架。该方法使用增强的异构图来统一电路组件和空间网格，从而更准确地模拟逻辑设计与物理实现之间的相互作用。在工业基准上的实验表明，VeriHGN在预测准确性方面优于或媲美最先进的方法。 AI

影响 该方法可以通过更早、更准确地预测布局拥塞来加速芯片设计。

排序理由 该集群包含一篇详细介绍芯片布局验证新方法的学术论文。[lever_c_demoted from research: ic=1 ai=0.7]

在 arXiv cs.AI 阅读 →

AI 生成摘要 · Google Gemini · 来自 1 个来源。 我们如何撰写摘要 →

新的VeriHGN框架预测芯片布局拥塞

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该集群包含一篇详细介绍芯片布局验证新方法的学术论文。[lever_c_demoted from research: ic=1 ai=0.7]
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报道来源 [1]

  1. arXiv cs.AI TIER_1 English(EN) · Runbang Hu, Bo Fang, Bingzhe Li, Yuede Ji ·

    VeriHGN：基于异构图的芯片布局验证拥塞预测

    arXiv:2603.11075v3 Announce Type: replace-cross Abstract: As Very Large Scale Integration (VLSI) designs continue to scale in size and complexity, layout verification has become a central challenge in modern Electronic Design Automation (EDA) workflows. In practice, congestion ca…

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