English(EN) Search-Guided Reasoning Trace Curation for Verilog Generation

新的MCTS-SFT框架增强了LLM的Verilog生成能力

作者 PulseAugur 编辑部 · [1 个来源] · 2026-10-31 04:00

研究人员开发了MCTS-SFT，一个旨在改进大型语言模型Verilog代码生成的新颖框架。该方法利用蒙特卡洛树搜索（MCTS）来指导推理轨迹的策展，将反馈从已完成的代码传播到早期的设计决策。该框架引入了Plan-MCTS，它在结构化的硬件设计计划上进行搜索，并证明在监督微调过程中保留这些显式计划可以显著增强下游学习并减少生成长度。 AI

影响这项研究可能带来更高效、更准确的硬件设计AI模型，从而加速专用芯片的开发。

排序理由该集群包含一篇详细介绍AI模型训练新方法的学术论文。[lever_c_demoted from research: ic=1 ai=1.0]

在 arXiv cs.AI 阅读 →

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Newsworthiness bucket: Tool; 该集群包含一篇详细介绍AI模型训练新方法的学术论文。[lever_c_demoted from research: ic=1 ai=1.0]
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报道来源 [1]

arXiv cs.AI TIER_1 English(EN) · Matthew DeLorenzo, Kevin Tieu, Prithwish Jana, Piyush Jha, Dileep Kalathil, Vijay Ganesh, Jeyavijayan Rajendran · 2026-10-31 04:00

Search-Guided Reasoning Trace Curation for Verilog Generation

arXiv:2610.37706v1 Announce Type: cross Abstract: Recent advances in large language models (LLMs) have improved Verilog generation. However, most training pipelines distill natural-language reasoning traces whose intermediate design decisions are weakly structured and are primari…

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Search-Guided Reasoning Trace Curation for Verilog Generation

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