English(EN) LATCH: LLM-Assisted Timing Closure Harness for Post-Route FPGA Optimisation

LLM辅助框架改进FPGA定时闭合

作者 PulseAugur 编辑部 · [1 个来源] · 2026-10-15 04:00

研究人员开发了LATCH，一个使用大型语言模型（LLMs）辅助后布线现场可编程门阵列（FPGAs）定时闭合的框架。研究比较了不同级别的LLM控制，发现专家编写的配方比直接EDA操作（71.4%）或LLM构建的过程（17.9%）具有更高的功能通过率（98.2%）。进一步的实验表明，分支探索和知识库引导的探索显著提高了最大频率增益，知识库方法达到了20.3%。 AI

影响这项研究展示了LLM在硬件设计中的一种新颖应用，有望加速优化过程并提高FPGA开发的效率。

排序理由学术论文，详细介绍了使用LLM进行FPGA优化的新框架。[lever_c_demoted from research: ic=1 ai=1.0]

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Newsworthiness bucket: Tool; 学术论文，详细介绍了使用LLM进行FPGA优化的新框架。[lever_c_demoted from research: ic=1 ai=1.0]
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报道来源 [1]

arXiv cs.AI TIER_1 English(EN) · Shu Gu, Matthew Youngman, Yuqin Zhao, Cristian Sestito, Ali Siddique, Ramesh Krishnamurthy, Danial Chitnis, Themis Prodromakis · 2026-10-15 04:00

LATCH：LLM辅助时序收敛工具，用于布线后FPGA优化

arXiv:2610.16625v1 Announce Type: new Abstract: Post-route FPGA timing closure remains expert-dependent and computationally expensive. We present LATCH (LLM-Assisted Timing Closure Harness), a two-layer framework that separates large language model (LLM) orchestration from determ…

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报道来源 [1]

LATCH：LLM辅助时序收敛工具，用于布线后FPGA优化

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