研究人员推出FPGN，一个旨在加速现场可编程门阵列（FPGA）上深度神经网络推理的新框架。FPGN通过使用面向硬件的可微分公式来训练查找表（LUT）神经元，并采用结构化拓扑以改善布线和时序，从而弥合了LUT原生学习与高效FPGA实现之间的差距。该系统包括一个延迟驱动的编译器，可自动进行设计空间探索和硬件生成，与现有方法相比，在延迟方面实现了显著降低，在LUT效率方面得到了提高。 AI
影响 该框架通过优化硬件实现，有可能显著加快对延迟敏感的AI应用的推理速度。
排序理由 该集群包含一篇详细介绍神经网络加速新框架的学术论文。
AI 生成摘要 · Google Gemini · 来自 3 个来源。 我们如何撰写摘要 →
完整方法见我们的编辑标准。
arXiv:2607.08427v1 Announce Type: cross Abstract: Achieving nanosecond-scale inference latency for deep neural networks (DNNs) has become a primary architectural concern for latency-critical applications. While Field-Programmable Gate Arrays (FPGAs) offer a promising substrate fo…
Achieving nanosecond-scale inference latency for deep neural networks (DNNs) has become a primary architectural concern for latency-critical applications. While Field-Programmable Gate Arrays (FPGAs) offer a promising substrate for low-latency inference, conventional FPGA acceler…
Achieving nanosecond-scale inference latency for deep neural networks (DNNs) has become a primary architectural concern for latency-critical applications. While Field-Programmable Gate Arrays (FPGAs) offer a promising substrate for low-latency inference, conventional FPGA acceler…