研究人员开发了一种用于U-Net卷积层的高能效硬件加速器，该加速器在现场可编程门阵列（FPGA）上实现。所提出的合并乘加（MMA）架构融合了运算，与传统的数字串行方法相比，可降低延迟并提高吞吐量。这种基于FPGA的解决方案提供了显著更高的能效，与基于CPU的推理相比，能效提高了近一个数量级，并且与现有的MSDF FPGA实现相比，能耗大大降低。 AI
影响 这项研究可能带来更节能的边缘设备AI推理，特别是在图像分割任务方面。
排序理由 该集群包含详细介绍在FPGA上加速CNN的新硬件架构的学术论文。
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This paper presents an energy-efficient hardware acceleration of the convolutional layers in the U-Net architecture for image segmentation, implemented on FPGA. While digit-serial arithmetic, particularly most-significant-digit-first (MSDF) techniques, offers a compact hardware f…
arXiv:2606.25562v1 Announce Type: cross Abstract: This paper presents an energy-efficient hardware acceleration of the convolutional layers in the U-Net architecture for image segmentation, implemented on FPGA. While digit-serial arithmetic, particularly most-significant-digit-fi…
This paper presents an energy-efficient hardware acceleration of the convolutional layers in the U-Net architecture for image segmentation, implemented on FPGA. While digit-serial arithmetic, particularly most-significant-digit-first (MSDF) techniques, offers a compact hardware f…