TimingLLM predicts post-synthesis timing from Verilog with high accuracy

Researchers have developed TimingLLM, a novel two-stage framework designed to predict post-synthesis timing in Verilog code without requiring synthesis tools. The first stage employs a fine-tuned LLM to generate structural-timing cues, while the second stage uses another LLM to predict worst negative slack (WNS) and total negative slack (TNS). This approach achieved high accuracy on the VerilogEval benchmark and demonstrated faster execution times compared to existing methods. AI

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IMPACT Introduces a new LLM-based approach for faster and more accurate hardware design timing prediction, potentially accelerating RTL iteration.

RANK_REASON This is a research paper detailing a new framework for timing prediction in hardware design.

Read on arXiv cs.LG →

• TimingLLM
• Verilog
• LLM
• WNS
• TNS
• VerilogEval
• R_WNS
• R_TNS
• MAPE

• paper
• model release