Verified floating-point types for ARCH HDL generated by LLMs

Researchers have developed and verified floating-point data types for the ARCH hardware description language, designed for generation by language models. The system ensures consistency across synthesizable SystemVerilog, SMT-LIB, and Lean 4 proof models for operators like comparisons, conversions, and arithmetic operations. Exhaustive verification was performed for simpler operators, while complex multiplier-based operations were proven correct against a round-to-nearest-even specification, with optimizations for performance and pipelineability. AI

IMPACT Enables more reliable hardware design generation from AI models, potentially speeding up hardware development cycles.

RANK_REASON Academic paper detailing formal verification of hardware description language components. [lever_c_demoted from research: ic=1 ai=1.0]

Read on arXiv cs.CL →

• ARCH HDL
• IEEE-754
• FP32
• SMT-LIB
• SystemVerilog
• Yosys

• paper
• infra

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