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New SPHBM4 standard aims to democratize HBM for AI chips

By PulseAugur Editorial · [6 sources] ·

JEDEC has announced a new standard, SPHBM4 (JESD330-4), designed to democratize High Bandwidth Memory (HBM) by enabling its use in standard packaging. This new standard allows for HBM assembly outside of specialized, supply-constrained advanced packaging facilities, potentially making HBM accessible for mid-tier AI chips, networking silicon, and gaming GPUs. SPHBM4 achieves this by reducing pin count while quadrupling signal speeds, which also necessitates the use of higher-layer count substrates and increases the physical size of chip packaging footprints, driving up demand and pricing for substrate materials. AI

IMPACT This new standard could lower the cost and increase the availability of high-performance memory for a wider range of AI accelerators and related hardware.

RANK_REASON Announcement of a new industry standard that significantly impacts AI chip manufacturing and component accessibility.

Read on X — SemiAnalysis →

AI-generated summary · Google Gemini · from 6 sources. How we write summaries →

New SPHBM4 standard aims to democratize HBM for AI chips

COVERAGE [6]

  1. X — SemiAnalysis TIER_1 English(EN) · SemiAnalysis_ ·

    The Bottom Line: SPHBM4 shifts the complex engineering burden of AI chips.

    The Bottom Line: SPHBM4 shifts the complex engineering burden of AI chips. Instead of buying a hyper-expensive, proprietary "Silicon Interposer + ABF Substrate" combo, chipmakers will shift entirely to buying ultra-large, high-layer ABF or even pull forward the adoption of glass

  2. X — SemiAnalysis TIER_1 English(EN) · SemiAnalysis_ ·

    🟠 It "democratizes" HBM.

    🟠 It "democratizes" HBM. Right now, HBM is locked behind a massive bottleneck: only a few specialized foundries have the advanced packaging tech (like TSMC CoWoS) to build them. This keeps HBM restricted to ultra-premium AI accelerators. SPHBM4 changes the game. By allowing

  3. X — SemiAnalysis TIER_1 English(EN) · SemiAnalysis_ ·

    🟠 It shoots layer counts through the roof.

    🟠 It shoots layer counts through the roof. Moving 32 Gbps signals directly across an organic substrate is an electrical nightmare. To prevent data corruption and electromagnetic interference, you can't just use a basic low layer count ABF substrate. SPHBM4 will force the use ht…

  4. X — SemiAnalysis TIER_1 English(EN) · SemiAnalysis_ ·

    🟠 It blows up the physical size of the substrate.

    🟠 It blows up the physical size of the substrate. Traditional HBM must sit microscopic millimeters away from the GPU because wide parallel signals degrade instantly over distance. Because SPHBM4 uses high-speed serial lanes, memory can sit up to 20mm away. This extra breathing

  5. X — SemiAnalysis TIER_1 English(EN) · SemiAnalysis_ ·

    The idea is simple: maintain HBM4 performance while drastically reducing the reliance on expensive, supply-constrained advanced packaging.

    The idea is simple: maintain HBM4 performance while drastically reducing the reliance on expensive, supply-constrained advanced packaging. How? By slashing the pin count to 1/5th but quadrupling signal speeds to 32 Gbps. This allows HBM-level bandwidth using standard substrates,…

  6. X — SemiAnalysis TIER_1 English(EN) · SemiAnalysis_ ·

    This last week JEDEC announced a new standard for SPHBM4: Standard Package High Bandwidth Memory (JESD330-4).

    This last week JEDEC announced a new standard for SPHBM4: Standard Package High Bandwidth Memory (JESD330-4). It utilizes the same DRAM stacks as HBM4, but swaps in a different buffer die. The goal? Enable HBM assembly in standard packaging and break the AI Advanced Packaging ht…

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