OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design
Researchers have released OpenRTLSet, a large, open-source dataset containing over 131,000 Verilog code samples for hardware design. The dataset includes Verilog, VHDL, and C/C++ translations, with natural language descriptions generated by the DeepSeek-R1 model. This resource aims to facilitate the fine-tuning of language models for Verilog code generation and demonstrates the potential of open-source approaches in hardware design. AI
IMPACT Enables development of AI tools for hardware design, potentially accelerating chip development cycles.