Open-source dataset released for AI-driven Verilog hardware design

Researchers have released OpenRTLSet, a large, open-source dataset containing over 131,000 Verilog code samples for hardware design. The dataset includes Verilog, VHDL, and C/C++ translations, with natural language descriptions generated by the DeepSeek-R1 model. This resource aims to facilitate the fine-tuning of language models for Verilog code generation and demonstrates the potential of open-source approaches in hardware design. AI

IMPACT Enables development of AI tools for hardware design, potentially accelerating chip development cycles.

RANK_REASON The cluster contains an academic paper describing a new dataset for LLM-based hardware design. [lever_c_demoted from research: ic=1 ai=1.0]

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• DeepSeek-R1
• Granite
• OpenRTLSet
• Qwen

• paper
• product
• other

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