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Open-source dataset released for AI-driven Verilog hardware design

By PulseAugur Editorial · [1 sources] ·

Researchers have released OpenRTLSet, a large, open-source dataset containing over 131,000 Verilog code samples for hardware design. The dataset includes Verilog, VHDL, and C/C++ translations, with natural language descriptions generated by the DeepSeek-R1 model. This resource aims to facilitate the fine-tuning of language models for Verilog code generation and demonstrates the potential of open-source approaches in hardware design. AI

IMPACT Enables development of AI tools for hardware design, potentially accelerating chip development cycles.

RANK_REASON The cluster contains an academic paper describing a new dataset for LLM-based hardware design. [lever_c_demoted from research: ic=1 ai=1.0]

Read on arXiv cs.CL →

AI-generated summary · Google Gemini · from 1 sources. How we write summaries →

Open-source dataset released for AI-driven Verilog hardware design

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The cluster contains an academic paper describing a new dataset for LLM-based hardware design. [lever_c_demoted from research: ic=1 ai=1.0]
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COVERAGE [1]

  1. arXiv cs.CL TIER_1 Norsk(NO) · Jinghua Wang, Lily Jiaxin Wan, Sanjana Pingali, Scott Smith, Manvi Jha, Shalini Sivakumar, Xing Zhao, Kaiwen Cao, Deming Chen ·

    OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design

    arXiv:2606.10285v1 Announce Type: new Abstract: OpenRTLSet introduces the largest fully open-source dataset for hardware design, offering over 131,000 diverse Verilog code samples to the research community and industry. Our dataset uniquely combines Verilog code from GitHub repos…

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