ESBMC-PLC: Formal Verification of IEC 61131-3 Ladder Diagram Programs Using SMT-Based Model Checking
Researchers have developed ESBMC-PLC, a novel open-source formal verifier designed to analyze IEC 61131-3 ladder diagram programs, commonly used in safety-critical industrial applications. This tool translates ladder logic into an intermediate representation and models the PLC scan cycle to check safety properties using SMT-based bounded model checking. Evaluations on various benchmarks, including deployed PLCs, demonstrate ESBMC-PLC's effectiveness in identifying bugs and verifying properties with high accuracy and speed. AI