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New tools enable formal verification of industrial PLC ladder diagram programs

Researchers have developed ESBMC-PLC and Graph-ESBMC-PLC, new tools for formally verifying industrial control programs written in the IEC 61131-3 Ladder Diagram (LD) format. These tools translate graphical LD programs into an intermediate representation that can be processed by SMT-based model checkers, addressing a gap in existing verification methods. The systems have been evaluated on various benchmarks, demonstrating their ability to correctly classify programs, find bugs, and provide proofs, all within efficient timeframes. AI

IMPACT Enables more robust verification of safety-critical industrial control systems, potentially reducing errors and improving reliability.

RANK_REASON The cluster contains two academic papers introducing new software tools for formal verification of a specific type of industrial programming language. [lever_c_demoted from research: ic=2 ai=0.4]

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New tools enable formal verification of industrial PLC ladder diagram programs

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The cluster contains two academic papers introducing new software tools for formal verification of a specific type of industrial programming language. [lever_c_demoted from research: ic=2 ai=0.4]
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COVERAGE [3]

  1. arXiv cs.CL TIER_1 English(EN) · Pierre Dantas, Lucas Cordeiro, Waldir Junior ·

    Graph-ESBMC-PLC: Formal Verification of Graphical PLCopen XML Ladder Diagram Programs Using SMT-Based Model Checking

    arXiv:2606.18941v1 Announce Type: cross Abstract: PLCopen XML defines two encoding formats for IEC 61131-3 Ladder Diagram programs: a textual encoding using elements, and a graphical encoding that represents rung logic as a directed graph of localId/refLocalId connections. ESBMC-…

  2. arXiv cs.CL TIER_1 English(EN) · Waldir Junior ·

    Graph-ESBMC-PLC: Formal Verification of Graphical PLCopen XML Ladder Diagram Programs Using SMT-Based Model Checking

    PLCopen XML defines two encoding formats for IEC 61131-3 Ladder Diagram programs: a textual encoding using <rung> elements, and a graphical encoding that represents rung logic as a directed graph of localId/refLocalId connections. ESBMC-PLC supported the textual format but parsed…

  3. arXiv cs.CL TIER_1 English(EN) · Pierre Dantas, Lucas Cordeiro, Waldir Junior ·

    ESBMC-PLC: Formal Verification of IEC 61131-3 Ladder Diagram Programs Using SMT-Based Model Checking

    arXiv:2606.15461v1 Announce Type: new Abstract: PLCs execute safety-critical programs across industrial sectors. The dominant PLC notation, ladder diagram (LD) per IEC 61131-3, remains absent from formal verification: SMT-based model checkers cannot process LD's rung-and-coil gra…