IEC 61131-3
PulseAugur coverage of IEC 61131-3 — every cluster mentioning IEC 61131-3 across labs, papers, and developer communities, ranked by signal.
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New benchmark suite targets formal verification of industrial PLC programs
Researchers have developed a new benchmark suite for formally verifying IEC 61131-3 ladder diagram programs, addressing a lack of standard evaluation tools in the field. This suite includes 50 programs across ten indust…
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New verification method detects hidden malicious logic in industrial controllers
Researchers have developed a new formal verification approach called ESBMC-LLB to detect malicious logic, known as Ladder Logic Bombs (LLBs), hidden within Programmable Logic Controller (PLC) programs. This method utili…
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New framework enhances PLC formal verification with broader language support
Researchers have developed ESBMC-PLC+, a new framework for formally verifying Programmable Logic Controller (PLC) programs. This successor to PLCverif addresses limitations by supporting Ladder Diagram (LD) and Structur…
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New tools enable formal verification of industrial PLC ladder diagram programs
Researchers have developed ESBMC-PLC and Graph-ESBMC-PLC, new tools for formally verifying industrial control programs written in the IEC 61131-3 Ladder Diagram (LD) format. These tools translate graphical LD programs i…