high-performance computing
PulseAugur coverage of high-performance computing — every cluster mentioning high-performance computing across labs, papers, and developer communities, ranked by signal.
- 2026-05-15 research_milestone Publication of a paper detailing a new heuristic-based method for merging HPC traces to extend hardware counter coverage for ML performance prediction. 来源
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ADMIN Update newsletter offers weekly tech news and articles
ADMIN Update is a weekly newsletter offering free technical articles and news. It covers a range of topics including AI, DevOps, HPC, security, and job opportunities. The newsletter aims to keep subscribers informed abo…
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AEM and ASE partner for AI/HPC testing, ASE invests S$12M
AEM and ASE have formed a strategic partnership to enhance testing solutions for artificial intelligence and high-performance computing. As part of this collaboration, ASE is investing S$12 million into AEM. This allian…
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HPC trace merging framework expands hardware counter coverage for ML
Researchers have developed a new heuristic-based method to merge High-Performance Computing (HPC) execution traces, aiming to expand the coverage of hardware counters available for machine learning-based performance pre…
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TSMC forecasts $1.5T chip market by 2030, driven by AI
Taiwan Semiconductor Manufacturing Company (TSMC) projects the global semiconductor market will surpass $1.5 trillion by 2030, a significant increase from previous forecasts. The company anticipates that artificial inte…
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Quantum-inspired eigensolver slashes parameters, boosts performance for quantum chemistry
Researchers have developed a new quantum-inspired eigensolver called GQKAE, designed to improve the efficiency of high-performance computing in quantum chemistry. This model replaces traditional feed-forward networks wi…
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Piper framework boosts MoE model training efficiency with resource modeling
A new framework called Piper has been developed to address the challenges of training large Mixture-of-Experts (MoE) models on high-performance computing (HPC) platforms. Piper utilizes resource modeling to optimize tra…
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Memory giants push new MRDIMM standard for AI, HPC servers
Major memory manufacturers Samsung Electronics, SK Hynix, and Micron are nearing completion of the next-generation server DRAM module standard, MRDIMM. This new standard is optimized for AI and high-performance computin…
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FedQueue protocol optimizes federated learning for HPC facilities
Researchers have developed FedQueue, a novel protocol designed to optimize federated learning across multiple High-Performance Computing (HPC) facilities. This system addresses the significant delays caused by batch sch…
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FedQueue protocol improves federated learning across HPC facilities
Researchers have developed FedQueue, a new protocol designed to improve federated learning across multiple high-performance computing (HPC) facilities. This method addresses challenges posed by stochastic delays from ba…
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Free Pascal and BLAS offer deterministic HPC for SLM projects
A user on Mastodon is exploring the use of BLAS, a set of Fortran-based matrix routines, for their Small Language Model (SLM) project. They express a preference for Free Pascal over languages like C, Python, Rust, and C…
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TSMC accelerates expansion plans, doubling production speed for 2nm chips to meet AI demand.
Taiwan Semiconductor Manufacturing Company (TSMC) is accelerating its expansion plans to meet surging demand for AI and high-performance computing. The company is advancing its production capacity at double the usual pa…
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AI's evolution presents new opportunities for HPC users and facilities
The rapid evolution of AI is prompting questions about its impact on high-performance computing (HPC) users and facilities. Specifically, there's a discussion on which segments of the HPC community stand to gain the mos…
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Multi-Plane HyperX network offers lower latency and cost for AI and HPC systems
Researchers have introduced the Multi-Plane HyperX network architecture, designed to improve the efficiency of large-scale AI and High-Performance Computing (HPC) systems. This new architecture extends multi-plane netwo…