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English(EN) CRAM-ER: Error-Resilient Spintronic Computational Random Access Memory for Scalable In-Memory Computation

新的 CRAM-ER 架构提升了 DNN 的内存内计算性能

研究人员开发了一种名为 CRAM-ER 的新架构,以提高深度神经网络内存内计算的效率和可扩展性。该方法将基于自旋电子的计算随机存取存储器 (CRAM) 与 CMOS 加法器相结合,以减轻 MRAM 开关固有的错误。该系统旨在通过降低与传统 CPU/GPU 设置相比的延迟和能耗来加速矩阵向量乘法,这是 DNN 中的一项关键操作。 AI

影响 这种新颖的架构可以显著降低运行深度神经网络的能耗和延迟成本。

排序理由 这是一篇详细介绍用于人工智能计算的新型硬件架构的研究论文。[lever_c_demoted from research: ic=1 ai=1.0]

在 arXiv cs.AI 阅读 →

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新的 CRAM-ER 架构提升了 DNN 的内存内计算性能

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这是一篇详细介绍用于人工智能计算的新型硬件架构的研究论文。[lever_c_demoted from research: ic=1 ai=1.0]
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报道来源 [1]

  1. arXiv cs.AI TIER_1 English(EN) · Sohan Salahuddin Mugdho, Md. Shahedul Hasan, Brahmdutta Dixit, Yang Lv, Jian-Ping Wang, Cheng Wang ·

    CRAM-ER:面向可扩展内存内计算的抗错误自旋电子计算随机存取存储器

    arXiv:2606.02781v1 Announce Type: cross Abstract: Deep neural networks (DNNs) have achieved state-of-the-art performance across diverse domains. However, typical Von Neumann compute paradigms face severe memory bottlenecks. Emerging near-memory and compute-in-memory approaches al…