English(EN) Here's the trap. When the chip is the whole wafer, you can't shrink your way to more SRAM and you can't make the wafer bigger. The only lever left is reallocati

Cerebras探索晶圆堆叠以提升AI芯片内存

作者 PulseAugur 编辑部 · [4 个来源] · 2026-06-02 21:00

Cerebras正在开发一种晶圆堆叠技术来增强其AI芯片，以解决SRAM的扩展限制。该方法涉及将第二个晶圆（可能包含额外的SRAM或计算能力）堆叠在其现有的Wafer Scale Engine (WSE)之上。尽管面临显著的热机械和堆叠挑战，这项创新旨在克服单个晶圆上内存和计算之间的权衡。 AI

影响 Cerebras的晶圆堆叠技术有望克服SRAM扩展限制，从而可能实现更强大的AI硬件。

排序理由该集群讨论了一种新颖的芯片设计和制造技术方法，这是一种研发形式。

在 X — SemiAnalysis 阅读 →

AI 生成摘要 · Google Gemini · 来自 4 个来源。我们如何撰写摘要 →

报道来源 [4]

X — SemiAnalysis TIER_1 English(EN) · SemiAnalysis_ · 2026-06-02 21:00

Cerebras has an escape: wafer-on-wafer bonding a second wafer to add SRAM or compute. They're seriously exploring it, already showing a DRAM wafer hybrid bonded

Cerebras has an escape: wafer-on-wafer bonding a second wafer to add SRAM or compute. They're seriously exploring it, already showing a DRAM wafer hybrid bonded onto the WSE for more fast memory. There are real thermo-mechanical and bond-wave challenges to clear, but going beyond
X — SemiAnalysis TIER_1 English(EN) · SemiAnalysis_ · 2026-06-02 21:00

Here's the trap. When the chip is the whole wafer, you can't shrink your way to more SRAM and you can't make the wafer bigger. The only lever left is reallocati

Here's the trap. When the chip is the whole wafer, you can't shrink your way to more SRAM and you can't make the wafer bigger. The only lever left is reallocating area, and more SRAM means less compute. A zero-sum tradeoff on silicon that's already maxed out. (3/4)
X — SemiAnalysis TIER_1 English(EN) · SemiAnalysis_ · 2026-06-02 21:00

Why the need for another wafer? SRAM has stopped scaling. That's a problem when SRAM is the whole pitch and 50% of the wafer. It's already on their roadmap: WSE

Why the need for another wafer? SRAM has stopped scaling. That's a problem when SRAM is the whole pitch and 50% of the wafer. It's already on their roadmap: WSE-1 shipped 18GB of SRAM, WSE-2 jumped to 40GB, a healthy 2.2x. But WSE-3 advanced to just 44GB, a 10% gain across a full…
X — SemiAnalysis TIER_1 English(EN) · SemiAnalysis_ · 2026-06-02 21:00

Cerebras did what the industry calls impossible: turned an entire 46,225mm² wafer into one chip. Defects on silicon that big are inevitable, so they built in re

Cerebras did what the industry calls impossible: turned an entire 46,225mm² wafer into one chip. Defects on silicon that big are inevitable, so they built in redundancy and custom per-batch masks that route around every bad core, landing near 100% usable wafers. The results: http…

报道来源 [4]

Cerebras has an escape: wafer-on-wafer bonding a second wafer to add SRAM or compute. They're seriously exploring it, already showing a DRAM wafer hybrid bonded

Here's the trap. When the chip is the whole wafer, you can't shrink your way to more SRAM and you can't make the wafer bigger. The only lever left is reallocati

Why the need for another wafer? SRAM has stopped scaling. That's a problem when SRAM is the whole pitch and 50% of the wafer. It's already on their roadmap: WSE

Cerebras did what the industry calls impossible: turned an entire 46,225mm² wafer into one chip. Defects on silicon that big are inevitable, so they built in re

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