HPC trace merging framework expands hardware counter coverage for ML

Researchers have developed a new heuristic-based method to merge High-Performance Computing (HPC) execution traces, aiming to expand the coverage of hardware counters available for machine learning-based performance prediction. This technique addresses the limitation of collecting a restricted set of hardware counters simultaneously by merging traces from multiple runs, each with different counters. The approach matches computation bursts across executions using MPI structure, timing, and communication patterns to create a unified dataset with a richer feature space for training ML models without manual counter selection. Validation on the MareNostrum5 machine demonstrated that the merged counters maintain acceptable accuracy for various applications and kernels. AI

影响 Enables more comprehensive hardware counter data for ML models, potentially improving the accuracy of HPC performance predictions.

排序理由 Publication of an academic paper on a novel methodology for HPC trace analysis. [lever_c_demoted from research: ic=1 ai=1.0]

在 arXiv cs.LG 阅读 →

• HPC
• Machine Learning
• Marc Clascà Ramírez
• MareNostrum5

• 论文
• 基础设施

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