English(EN) Massively Parallel Reinforcement Learning with a Chaotic Reconfigurable Clockless Chip

新型混沌芯片架构实现大规模并行强化学习

作者 PulseAugur 编辑部 · [1 个来源] · 2026-09-28 22:31

研究人员开发了一种新颖的强化学习硬件架构，该架构利用无时钟、可重构芯片上的异步布尔网络。该设计生成混沌布尔转换的并行流，从而实现对可扩展性至关重要的统计独立熵源。该系统成功地在1024臂老虎机问题上展示了并行决策，突破了先前的硬件限制，并显示出改进的幂律缩放。此外，该架构已扩展到5120个并行通道，实现了2.14 TS/s的总样本生成速率，为高吞吐量决策加速器铺平了道路。 AI

影响这种新颖的硬件架构可以显著提高强化学习应用的能效和可扩展性。

排序理由这是一篇详细介绍强化学习新硬件架构的研究论文。[lever_c_demoted from research: ic=1 ai=1.0]

在 arXiv cs.NE (Neural & Evolutionary) 阅读 →

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arXiv cs.NE (Neural & Evolutionary) TIER_1 English(EN) · Damien Rontani · 2026-09-28 22:31

具有混沌可重构无时钟芯片的大规模并行强化学习

Hardware accelerators based on physical dynamical systems offer an attractive route toward energy-efficient reinforcement learning applications. However, their scalability is challenging because it requires many statistically independent entropy sources. Here, we introduce a quas…

本文如何被排名

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具有混沌可重构无时钟芯片的大规模并行强化学习

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