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English(EN) A Time-Based Readout for Vector-Matrix Multiplication in Fully Analog Memristive SNNs

新型模拟读出架构提升SNN效率

研究人员开发了一种利用电压到时间转换的新型脉冲神经网络(SNN)模拟读出架构。该方法旨在通过消除对传统电流模式求和和缩放电路的需求来提高面积和能源效率。在130 nm CMOS技术中的仿真证明了该架构在SNN推理中的有效性,包括成功的数字分类。 AI

影响 这项研究可能为AI推理带来更节能的硬件,特别适用于边缘设备。

排序理由 该集群包含一篇详细介绍神经网络新技术方法的学术论文。[lever_c_demoted from research: ic=1 ai=1.0]

在 arXiv cs.AI 阅读 →

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新型模拟读出架构提升SNN效率

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该集群包含一篇详细介绍神经网络新技术方法的学术论文。[lever_c_demoted from research: ic=1 ai=1.0]
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完整方法见我们的编辑标准

报道来源 [1]

  1. arXiv cs.AI TIER_1 English(EN) · Elia Mateu-Barriendos, \'Alvaro G\'omez-Pau, Josep Rius, Daniel Arum\'i, Rosa Rodr\'iguez-Monta\~n\'es, Salvador Manich ·

    全模拟忆阻器脉冲神经网络中的基于时间的读出用于向量-矩阵乘法

    arXiv:2609.11713v1 Announce Type: cross Abstract: Artificial neural networks rely on vector-matrix multiplications (VMMs), whose implementation in von Neumann architectures is dominated by costly data movement between memory and processing units. Spiking neural networks (SNNs) mi…