resistive random-access memory
PulseAugur coverage of resistive random-access memory — every cluster mentioning resistive random-access memory across labs, papers, and developer communities, ranked by signal.
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Ex-Graphcore President Tao Lu joins MemSilicon to develop LPU chips
MemSilicon, an AI chip startup, has secured over 400 million yuan in Series A funding, with notable investors including Bo Yuan Capital and Bosch Ventures. The company also announced the appointment of Tao Lu, former Pr…
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MemSilicon tapes out 1Gb RRAM chip with 1T4R architecture
MemSilicon has announced the successful tape-out of its MountTai 2026 chip, a 1Gb RRAM (resistive random-access memory) device utilizing a 1T4R (one transistor, four resistors) architecture. This marks a significant mil…
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Research paper examines fault vulnerability in ReRAM-based PIM CNN accelerators
A new research paper explores the vulnerability of ReRAM-based Process-in-Memory (PIM) accelerators to faults, which can degrade the accuracy of deep convolutional neural networks (CNNs). The study developed a fault inj…
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New FPGA Architecture Boosts ML Inference Efficiency
Researchers have developed a novel FPGA architecture called NIFA that enhances deep learning inference efficiency. This architecture integrates an ADC-free In-Memory Computing (IMC) block using analog content-addressabl…
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New toolkit optimizes neural network inference on RRAM crossbars
Researchers have developed CIM-Explorer, a new toolkit designed to optimize the performance of Binary and Ternary Neural Networks (BNNs and TNNs) when run on Resistive Random-Access Memory (RRAM) crossbars. This tool ad…
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New framework optimizes ML workload partitioning for CPU-CIM systems
Researchers have developed a new framework for partitioning machine learning workloads between central processing units (CPUs) and Computing-in-Memory (CIM) accelerators. This framework addresses limitations in existing…
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New framework ApproxHDC optimizes Hyperdimensional Computing with compiler-driven approximations
Researchers have developed ApproxHDC, a novel framework that leverages compiler-driven approximation tuning to enhance the efficiency of Hyperdimensional Computing (HDC) workloads. This approach is designed to address t…
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New Finetuning Method Adapts DNNs for ReRAM In-Memory Computing
Researchers have developed a new finetuning method to adapt deep neural networks for deployment on ReRAM-based in-memory computing hardware. This approach addresses the challenges of I-V non-linearity and retention erro…
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RRAM-based RBF Neuron Hardware Achieves 89.1% MNIST Accuracy
Researchers have developed a novel hardware implementation for a Radial Basis Function (RBF) neuron using Metal-Oxide Resistive RAM (RRAM) technology. This design, based on a custom Template piXeL (TXL) cell, acts as an…
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New compute-in-memory macro boosts edge AI inference efficiency
Researchers have developed E-ReCON, a novel compute-in-memory (CIM) macro designed for efficient AI inference on edge devices. This macro utilizes a compact ReRAM bitcell capable of performing multiplication for both co…