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UltraRISC unveils RVA23-compliant UR-CP400 RISC-V core for 2027

UltraRISC Technology has unveiled its UR-CP400, a RISC-V processor core IP that adheres to the RVA23 standard. This core features an 8-wide out-of-order execution pipeline. The company projects that the UR-CP400 will be available in the first quarter of 2027, and it has demonstrated performance exceeding 22/GHz on SPECint2006 benchmarks using an FPGA prototype. AI

IMPACT This development in RISC-V architecture could eventually influence the hardware landscape for AI development, offering alternative platforms for specialized AI acceleration.

RANK_REASON This is a product release for a processor core IP, which falls under the 'tool' category as it's a component for building systems rather than a frontier model or significant industry-wide event.

Read on Pandaily →

AI-generated summary · Google Gemini · from 1 sources. How we write summaries →

UltraRISC unveils RVA23-compliant UR-CP400 RISC-V core for 2027

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Signal score
0 / 100
Composite score across the factors below. Higher = stronger signal that this story matters right now.
Newsworthiness bucket
Tool
This is a product release for a processor core IP, which falls under the 'tool' category as it's a component for building systems rather than a frontier model or significant industry-wide event.
Source corroboration
Single-source cluster
Only one publisher covered this so far. Single-source stories can still rank when the publisher is high-authority, but they lack cross-source corroboration.
Topics
product, infra
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High
Clearly on-topic for AI-industry coverage.
Story freshness
3 days old
Aged out of breaking-news scoring windows; ranking reflects the durable signal from the full source set.

Full methodology in our editorial standards.

COVERAGE [1]

  1. Pandaily TIER_1 English(EN) · [email protected] (Pandaily) ·

    UltraRISC Shows UR-CP400 RISC-V Core IP: RVA23, 8-Wide Out-of-Order, Delivery in Q1 2027

    Shanghai-based UltraRISC Technology showed UR-CP400, an RVA23-compliant RISC-V processor core IP with 8-wide out-of-order issue. It quotes SPECint2006 above 22/GHz on an FPGA prototype.