Reinforcement learning optimizes VLSI chip power delivery networks

Researchers have developed a reinforcement learning framework to optimize power delivery networks (PDNs) in very-large-scale integration (VLSI) chips. This new method uses workload-aware power traces to adapt PDN resource allocation, reducing the average normalized PDN area by 47% while maintaining integrity constraints. The reinforcement learning agent, specifically a Deep Q-Network, achieves comparable optimization quality to simulated annealing but is significantly faster, completing optimizations approximately 26 times quicker. AI

IMPACT This approach could lead to more efficient and smaller VLSI chips by reducing over-provisioning in power delivery networks.

RANK_REASON The item is a research paper detailing a novel method for optimizing VLSI chip power delivery networks using reinforcement learning. [lever_c_demoted from research: ic=1 ai=1.0]

Read on Hugging Face Daily Papers →

• Deep Q-Network
• electromigration
• PARSEC
• reinforcement learning
• very-large-scale integration

• paper
• infra

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