very-large-scale integration
PulseAugur coverage of very-large-scale integration — every cluster mentioning very-large-scale integration across labs, papers, and developer communities, ranked by signal.
-
New X-OPM system offers explainable on-chip power modeling
Researchers have developed X-OPM, a novel system for explainable automatic digital on-chip power modeling. This framework uses a human-in-the-loop workflow and combines tree-based models for feature interaction with lin…
-
Reinforcement learning optimizes VLSI chip power delivery networks
Researchers have developed a reinforcement learning framework to optimize power delivery networks (PDNs) in very-large-scale integration (VLSI) chips. This new method uses workload-aware power traces to adapt PDN resour…
-
LLM-designed algorithms boost VLSI macro legalization efficiency
Researchers have developed MacroAgent, a novel framework designed to improve macro legalization in very large-scale integration (VLSI) designs. This four-stage approach utilizes Large Language Models (LLMs) to generate …
-
New VLSI architecture targets sustainable AI with dynamic precision scaling
Researchers have developed Eco-SoC, a novel VLSI architecture designed for sustainable artificial intelligence. This architecture features a Dynamic Precision-Scaling Logic (DPSL) framework that dynamically adjusts bit-…
-
Intel details future chip tech: CFET, GaN integration, and new interconnects
Intel has unveiled advancements in its chip manufacturing technology, including the Intel 18A-P process node which offers improved performance and power efficiency over its predecessor. The company also detailed progres…
-
New VeriHGN framework predicts chip layout congestion
Researchers have developed VeriHGN, a new framework for predicting congestion in chip layout verification. This approach uses an enhanced heterogeneous graph to unify circuit components and spatial grids, allowing for a…
-
AI agents curate open-source VLSI benchmark suite
Researchers have introduced HighTide, a new benchmark suite for Very Large Scale Integration (VLSI) design that utilizes AI agents for curation. This open-source suite supports multiple design languages and technology n…
-
Graph Neural Networks accelerate VLSI design with faster capacitance modeling
Researchers have developed GNN-Ceff, a novel method utilizing Graph Neural Networks for post-layout effective capacitance modeling in VLSI design. This approach aims to improve the accuracy and speed of static timing an…